TAS3208IPZP datasheet(10/79 Pages) TI1

10 / 79 page

LRCLK (note reversed phase)

SCLK

2-Channel I S (Philips Format) Stereo Input

Left Channel

Right Channel

LSB

MSB

LSB

32 clks

24-Bit Mode

20-Bit Mode

16-Bit Mode

23 22 21 20 19 18 17 16 15 14 13

12 11

23 22 21 20 19 18 17 16 15 14 13

12 11

19 18 17 16 15 14 13

12 11

15 14 13

12 11

19 18 17 16 15 14 13

12 11

15 14 13

12 11

TAS3208

SLES201E

– JANUARY 2007 – REVISED MARCH 2011

www.ti.com

MCLKOUT, SCLKOUT, and LRCLKOUT are passed through from the clock inputs MCLKIN, SCLKIN, and

LCLKIN.

•

MCLKIN 256

× Fs is supplied externally.

•

SCLKIN 64

× Fs is supplied externally.

•

LRCLKIN Fs is supplied externally.

NOTE

In slave mode, all incoming serial audio data must be synchronous to an incoming

LRCLKIN of 32, 44.1, or 48 kHz. The TAS3208 does not support the use of an external

(i.e., 24-MHz) clock input into XTALI.

Digital Audio Data Formats

Serial data is input on pins SDIN3

–SDIN1 on the TAS3208, allowing up to six channels of digital audio input. The

TAS3208 supports 16-, 20-, or 24-bit data in left, right, or I2S serial data format. By default, all TAS3208 serial

digital inputs are configured in the 24-bit I2S format. The serial data input format is configurable via the

SAP/Clock Settings register.

Serial data is output on pins SDOUT1 and SDOUT2, allowing up to four channels of digital audio output. By

default, the SDOUT data format is 24-bit I2S format at the same data rate as the input. The SDOUT1 and

SDOUT2 outputs use SCLKOUT and LRCLKOUT signals to provide synchronization. SDOUT2 is multiplexed

with an SPDIF output.

NOTE

To avoid audio artifacts, I2C commands to reconfigure the serial audio port (SAP) should

not be issued as stand-alone commands, rather they should be accompanied by mute and

unmute commands.

The TAS3208 uses the SCLK as a reference for both input and output samples. The negative edge of SCLK is

used to output a new data bit, whereas the positive edge of SCLK is used to sample incoming serial data.

Discrete I2S Timing

I2S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. The LRCLK is LOW for the left channel and HIGH for the right channel. A bit clock running at 64

Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to

the first bit of data on the data lines. The data is written most significant bit (MSB) first and is valid on the rising

edge of bit clock. The TAS3208 will mask unused trailing data bit positions.

All data are presented in 2s-complement form with MSB first.

Figure 5. SAP I2S 64

× Fs Format

Submit Documentation Feedback

Product Folder Link(s): TAS3208

TAS3208IPZP 数据表(PDF) 10 Page - Texas Instruments

TAS3208IPZP 数据表(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

数据表下载

链接网址

TAS3208IPZP 数据表(PDF) 10 Page - Texas Instruments

TAS3208IPZP 数据表(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

数据表 下载

链接网址

数据表下载