TAS3208IPZP datasheet(64/79 Pages) TI1

64 / 79 page

TAS3208

SLES201E

– JANUARY 2007 – REVISED MARCH 2011

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Table 28. Analog Busy(1)

ANALOG BUSY FLAG

ABSY

Analog is busy

Analog not busy

(1)

Default values are shown in italics.

Analog control sequence takes time (maximum approximately 500 ms for headphone power up). This busy flag

indicates whether the analog control sequence is running or not.

Table 29. I2C Bus Error(1)

I2C BUS ERROR

BUSE

Bus error

No bus error

(1)

Default values are shown in italics.

If an I2C bus error occurs, this flag will be set. Only the host microcontroller can clear this flag by writing 0 to this

bit. I2C bus error status is read from ESFR 0xC5, bit 6, and is cleared by ESFR 0xC7, bit 6.

I2C RAM Load Control and Data Registers (0x04 and 0x05)

The I2C memory load port permits the system controller to load the TAS3208 memories as an alternative to

having the TAS3208 load its memory from an external EEPROM.

The transfer is performed by writing to two I2C registers. The first register is a 8-byte register than holds the

checksum, memory to be written, starting address, and number of data bytes to be transferred. The second

The memory load operation starts with the first register being set. Then the data is written into the second

bytes are written, which constrain the 2-byte checksum. At that point, the transfer is complete and status of the

operation is reported in the Status register.

NOTE

Once the microprogram memory has been loaded, further updates to this memory are

inhibited until the device is reset.

When the first I2C slave download register is written by the system controller, the TAS3208 updates the Status

when the operation complete and a valid checksum has been received.

For example, when the microprogram memory is being loaded, the TAS3208 will set a microprogram memory

error indication in the Status register at the start of the sequence. When the last byte of the microprogram

memory and checksum is received, the TAS3208 will clear the microprogram memory error indication. This

enables the TAS3208 to preserve any error status indications that occur as a result of incomplete transfers of

data/ checksum error during a series of data and program memory load operations.

The checksum is always contained in the last two bytes of the data block.

The I2C slave download is terminated when a termination header with a zero-length byte count field is received.

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