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TAS3208IPZP 数据表(PDF) 54 Page - Texas Instruments

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部件名 TAS3208IPZP
功能描述  DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
PDF  79 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TAS3208IPZP 数据表(HTML) 54 Page - Texas Instruments

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TAS3208
SLES201E
– JANUARY 2007 – REVISED MARCH 2011
www.ti.com
Table 15. DSP Data RAM Block Structure
STARTING
DATA BLOCK FORMAT
SIZE
VALUE
NOTES
BYTE
Checksum MSB
0
2 bytes
Checksum of byte 2 through N + 12
Checksum LSB
Header ID byte 1
0x00
2
2 bytes
Must be 0x001F
Header ID byte 2
0x1F
4
Memory to be loaded
1 byte
0x04
Microprogram RAM or micro external data RAM
5
0x00
1 byte
0x00
Unused
Start memory address MSB
6
2 bytes
If this is a termination header, this value is 0000.
Start memory address LSB
Total number of byte transferred MSB
8
2 bytes
Header (12) + data (N) + checksum (4)
Total number of byte transferred LSB
10
0x00
1 byte
0x00
Unused
11
0x00
1 byte
0x00
Unused
Data byte 1 (LSB)
Data word 1 D7
–D0
Data byte 2
D15
–D8
Data byte 3
D23
–D16
12
6 bytes
Data byte 4 (MSB)
D31
–D24
Data byte 5
D39
–D32
Data byte 6 (MSB)
D47
–D40
Data byte 7 (LSB)
Data byte 8
Data byte 9
18
6 bytes
Data word 2
Data byte 10
Data byte 11
Data byte 12 (MSB)
⋮
⋮
⋮
⋮
⋮
0x00
0x00
N + 12
6 bytes
Repeated checksum byte 2 through N +11
Checksum MSB
Checksum LSB
Slave I
2C Load RAM Block Formats
The slave I2C bus permits the system controller to load the TAS3208 memories as an alternative to using the
master download from an external memory device via the I2C master bus. The transfer is performed by writing to
two I2C registers (0x04 and 0x05). The first register holds the header information, and the second register holds
eight bytes of data. Figure 39 shows the I2C slave download flow.
I2C slave download register format are described in Table 16 to Table 20. The I2C slave download process is
terminated when a termination header with zero-length byte count field is received.
54
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Copyright
© 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS3208



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