TAS3208IPZP datasheet(47/79 Pages) TI1

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TAS3208

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SLES201E

– JANUARY 2007 – REVISED MARCH 2011

2C INTERFACE AND I/O CHARACTERISTICS OF SDA AND SCL BUS LINES FOR

STANDARD-MODE AND FAST-MODE I

2C BUS DEVICES

See Figure 38

STANDARD MODE

FAST MODE

UNIT

MIN

MAX

MIN

MAX

fSCL

SCL clock frequency

100

400(1)

kHz

Hold time, (repeated) Start condition. After this period, the

tHD;STA

0.6

µs

first clock pulse is generated.

tLOW

LOW period of SCL clock

4.7

1.3

µs

tHIGH

HIGH period of SCL clock

0.6

µs

tsu;STA

Setup time, repeated Start condition

4.7

0.6

µs

tsu;DAT

Data setup time

250

100(2)

Rise time, both SDA and SCL signals

1000

20 + 0.1

× Cb

(3)

300

Fall time, both SDA and SCL signals

300

20 + 0.1

× Cb

(3)

300

tsu;STO

Setup time, Stop condition

0.6

µs

tBUF

Bus free time between Stop and Start condition

4.7

1.3

µs

Capacitive load for each bus line

400

Noise margin at LOW level for each connected device

VnL

0.1

× VDD

0.1

× VDD

(including hysteresis)

Noise margin at HIGH level for each connected device

VnH

0.2

× VDD

0.2

× VDD

(including hysteresis)

Vhys

Hysteresis of Schmitt-trigger inputs

0.05

× VDD

Pulse width of spikes that must be suppressed by the

tSP

input filter

Input current each I/O pin with an input voltage

–10

–10(4)

10(4)

µA

between 0.1

× VDD and 0.9 × VDD max

Capacitance for each I/O pin

Output fall time from VIHmin to VILmax, with a bus

tof

250(5)

7 + 0.1

× Cb

(3)

250(5)

capacitance from 10 pF to 400 pF

(1)

In Master mode, the maximum I2C clock rate is 375 kHz.

(2)

A Fast-mode I2C bus device can be used in a Standard-mode I2C bus system, but the requirement tSU;DAT ≥ 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line.

(3)

Cb = Total capacitance of one bus line in pF

(4)

I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched off.

(5)

The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This

allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines, without exceeding the

maximum specified tf.

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