TNETV2501INPGF datasheet(30/197 Pages) TI1

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Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Host Port − Data Bus

HD[7:0]

I/O/Z

C, D, F,

G, H

The HD[7:0] pins of the Host Port serve one of two functions: parallel general-purpose

input/output (PGPIO) signals PGPIO[43:36] or host-port interface (HPI) data bus signals

HPI.HD[7:0]. The function of the HD[7:0] pins is determined by the state of the GPIO6 pin

during reset. The HD[7:0] pins are set to PGPIO[43:36] if GPIO6 is low during reset. The

HD[7:0] pins are set to HPI.HD[7:0] if GPIO6 is high during reset. The function of the

HD[7:0] pins will be set once the device is taken out of reset (RESET pin transitions from a

low to high state).

The HD[7:0] bus includes bus holders to reduce the static power dissipation caused by

floating, unused pins. The bus holders also eliminate the need for external bias resistors

on unused pins. When the bus goes into a high-impedance state, the bus holders keep the

address bus at the logic level that was most recently driven. The bus holders are enabled

at reset and can be enabled/disabled through the External Bus Control Register (XBCR).

PGPIO[43:36]

I/O/Z

Parallel general-purpose I/O. PGPIO[43:36] is selected when GPIO6 is low during

reset. The PGPIO[43:36] signals are configured as inputs after reset.

HPI.HD[7:0]

I/O/Z

Host data bus. HPI.HD[7:0] is selected when GPIO6 is high during reset. The

HPI.HD[7:0] signals are configured as inputs after reset.

The HPI will operate in multiplexed mode when GPIO6 is high during reset. In multiplexed

mode, an 8-bit data bus (HPI.HD[7:0]) carries both address and data. Each host cycle on

the bus consists of two consecutive 8-bit transfers.

Host Port − Control Pins

HC0

I/O/Z

C, F, G,

The HC0 pin of the Host Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO44 or host-port interface (HPI) signal HPI.HAS. The

function of the HC0 pin is determined by the state of the GPIO6 pin during reset. The HC0

pin is set to PGPIO44 if GPIO6 is low during reset. The HC0 pin is set to HPI.HAS if GPIO6

is high during reset. The function of the HC0 pin will be set once the device is taken out of

reset (RESET pin transitions from a low to high state).

PGPIO44

I/O/Z

C, F, G,

H, J

Parallel general-purpose I/O. PGPIO44 is selected when GPIO6 is low during reset.

The PGPIO44 signal is configured as an input after reset.

HPI.HAS

Host address strobe. HPI.HAS is selected when GPIO6 is high during reset. The

HPI.HAS signal is configured as an input after reset.

Hosts with multiplexed address and data pins may require HPI.HAS to latch the address in

the HPIA register. HPI.HAS is only available when the HPI is operating in multiplexed

mode.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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