TNETV2501INPGF datasheet(46/197 Pages) TI1

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Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.3.3 External Bus Selection Register (XBSR)

The External Bus Selection Register controls the mode of the Parallel Port Mux and Host Port Mux. The

Parallel Port Mux can be configured to support the 32-bit EMIF or to support parallel general-purpose I/O. The

Host Port Mux can be configured to support the HPI in 8-bit (multiplexed) mode or parallel general-purpose

I/O (PGPIO).

The XBSR configures the Parallel Port Mux and the Host Port Mux at reset based on the state of the GPIO6

pin at reset. When GPIO6 is high at reset, the Parallel Port Mux will be configured to support the 32-bit EMIF

and the Host Port Mux will be configured to support the HPI in 8-bit (multiplexed) mode. When GPIO6 is low

at reset, both the Parallel Port Mux and the Host Port Mux will be configured to support parallel

general-purpose I/O; the EMIF and HPI will be disabled in this mode. The Paralle/Host Port Mux Mode bit of

the XBSR will reflect the mode selected for the Parallel and Host Port Muxes.†

The clock to the EMIF module is disabled automatically when this module is not selected through the External

Bus Selection Register. Note that any accesses to disabled modules will result in a bus error if the PERITOEN

bit of the Time-Out Control Register is set to 1.

Reserved

R, 00000000

Reserved

(see NOTE)

Reserved

(see NOTE)

Reserved

Parallel /Host

Port Mux

Mode

R, 0000

R/W, 0

R, 0

R/W, GPIO6

LEGEND: R = Read, W = Write, n = value at reset

NOTE: This reserved bit must be kept as zero during any writes to XBSR.

Figure 3−3. External Bus Selection Register Layout (0x6C00)

† Modifying the XBSR to change the mode of the Parallel Port Mux and Host Port Mux after the 5501 has been brought out of reset is not

supported.

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