TNETV2501INPGF datasheet(57/197 Pages) TI1

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Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.7

Host-Port Interface (HPI)

The 5501 HPI provides an 8-bit parallel interface (multiplexed mode) to a host with the following features:

•

Host access to on-chip DARAM (excluding CPU memory-mapped registers)

•

16-bit address register with autoincrement capability for faster transfers

•

Multiple address/data strobes provide a glueless interface to a variety of hosts

•

HRDY signal for handshaking with host

The 5501 HPI can access the entire DARAM space of the 5501 (excluding memory-mapped CPU registers);

however, it does not have access to external memory of the peripheral I/O space. Furthermore, the HPI cannot

access internal DARAM space when the device is in reset. Note that all accesses made through the HPI are

word-addressed.

NOTE: No host access should occur when the HPI is placed in IDLE. The host cannot wake

up the DSP through the DSP_INT bit of the HPIC register when the DSP is in IDLE mode.

The 5501 HPI only supports data transfers in multiplexed 8-bit mode. In multiplexed mode, the host can only

send 8 bits of data at a time through the HD[7:0] bus; therefore, some extra steps have to be taken to read/write

from the 5501’s internal memory [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference

Guide (literature number SPRU620) for more information on the 5501 HPI].

The 5501 HPI has its own register set, therefore the HINT bit of CPU register ST3_55 is not used for

DSP-to-host interrrupts. The HINT bit in the Host Port Control Register (HPIC) should be used for DSP-to-host

interrupts.

A host must not initiate any transfer requests from the HPI while the HPI is being brought out of reset. As

described in Section 3.9.6, Reset Sequence, the C55x CPU and the peripherals are not brought out of reset

immediately after the RESET pin transitions from low to high. Instead, an internal counter stretches the reset

signal to allow enough time for the internal oscillator to stabilize and also to allow the reset signal to propagate

through different parts of the device. The IACK pin will go low for two CPU clock cycles to indicate that this

internal reset signal has been deasserted. A host must follow one of these two requirements before initiating

transfer requests from the HPI:

Keep the HPIENA pin low until the internal reset signal has been deasserted.

Keep the HCS, HDS1, and HDS2 pins inactive until the internal reset signal has been deasserted.

Note that when the HPI bootmode is used, the GPIO4 pin can also be used to determine when the internal

reset signal has been deasserted as this pin is used by the HPI to signal to the host that it is ready to receive

access requests.

TNETV2501INPGF 数据表(PDF) 57 Page - Texas Instruments

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