TNETV2501INPGF datasheet(39/197 Pages) TI1

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Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.1

Memory

The 5501 supports a unified memory map (program and data accesses are made to the same physical space).

The total on-chip memory is 32K words (16K 16-bit words of RAM and 16K 16-bit words of ROM).

3.1.1 On-Chip ROM

TMS320VC5501 incorporates 16K x16-bit of on-chip, one-wait-state maskable ROM that can be mapped into

program memory space. The on-chip ROM is located at the byte address range FF8000h−FFFFFFh when

MPNMC = 0 at reset. When MPNMC = 1 at reset, the on-chip ROM is disabled and not present in the memory

map, and byte address range FF8000h−FFFFFFh is directed to external memory space. MPNMC is a bit

located in the ST3 status register, and its status is determined by the logic level on the BOOTM[2:0] pins when

sampled at reset. If BOOTM[2:0] are set to 00h at reset, the MPNMC bit is set to 1 and the on-chip ROM is

disabled; otherwise, the MPNMC bit is cleared to 0 and the on-chip ROM is enabled. These pins are not

sampled again until the next hardware reset. The software reset instruction does not affect the MPNMC bit.

Software can be used to set or clear the MPNMC bit.

The ROM can be accessed by the program bus (P) and the two read data buses (C and D). The on-chip ROM

is a two-cycle-per-word memory access, except for the first word access, which requires four cycles.

The standard on-chip ROM contains a bootloader which provides a variety of methods to load application code

automatically after power up or a hardware reset. For more information, see Section 3.1.5, Boot Configuration.

A vector table associated with the bootloader is also contained in the ROM. A boot mode branch table is

included in the ROM which contains hard-coded jumps to the beginning of each boot mode code section in

the bootloader.

A sine look-up table is provided containing 256 values (crossing 360 degrees) expressed in Q15 format.

The standard on-chip ROM layout is shown in Table 3−1.

Table 3−1. On-Chip ROM Layout

STARTING BYTE ADDRESS

CONTENTS

FF_8000h

Bootloader Program

FF_ECAEh

Bootloader Revision Number

FF_ECB0h

Boot Mode Branch Table

FF_ED00h

Sine Table

FF_EF00h

Reserved

FF_FF00h

Interrupt Vector Table

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