TNETV2501INPGF datasheet(32/197 Pages) TI1

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Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

HPI Pins (Continued)

HINT

O/Z

F, G, H,

J, M

Host interrupt (from DSP to host). The HINT pin is used by the DSP to interrupt the host.

The HINT signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

HPIENA

C, L

HPI enable. The HPIENA pin must be dreiven high to enable the HPI for operation. If the

HPIENA pin is low, the HPI will be completely disabled and all HPI output pins will be in a

high-impedance state.

If the HPI is not needed, the HPIENA pin can be pulled low.

Interrupt and Reset Pins

INT[3:0]

C, L

Maskable external interrupts. INT0−INT3 are maskable interrupts.They are enabled

through the Interrupt Enable Registers (IER0 and IER1). All maskable interrupts are

globally enabled/disabled through the Interrupt Mode bit (INTM in ST1_55). INT0−INT3

can be polled and reset via the Interrupt Flag Registers (IFR0 and IFR1). All interrupts are

prioritized as shown in Table 3−75, Interrupt Table.

NMI/WDTOUT

I/O/Z

C, F, J,

Non-maskable external interrupt or Watchdog Timer output. The function of this pin is

controlled by the Timer Signal Selection Register (TSSR). By default, the NMI/WDTOUT

pin has the function of the NMI signal.

NMI is an external interrupt that cannot be masked by the Interrupt Enable Registers

(IER0 and IER1). When NMI is activated, the interrupt is always performed.

WDTOUT serves as an input and output pin for the Watchdog Timer.

IACK

O/Z

F, M

Interrupt acknowledge. IACK indicates the receipt of an interrupt and that the program

counter is fetching the interrupt vector location designated on the address bus. The IACK

pin is set to a value of ‘1’ during reset.

RESET

C, L

Device reset. RESET causes the digital signal processor (DSP) to terminate current

program execution. When RESET is brought to a high level, program execution begins by

fetching the reset interrupt service vector at the reset vector address FFFF00h

(IVPD:FFFFh). RESET affects various registers and status bits.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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