TNETV2501INPGF datasheet(72/197 Pages) TI1

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Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.9.5.7

Oscillator Divider1 Register (OSCDIV1) for CLKOUT3

This register controls the value of the divider OD1 for CLKOUT3. It does not go through the PLL path.

OD1EN

Reserved

R/W, 0

R, 0000000

Reserved

OSCDIV1

R, 000

R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−21. Oscillator Divider1 Register Layout (0x1C92)

Table 3−18. Oscillator Divider1 Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

OD1EN

R/W

Oscillator divider OD1 enable

OD1EN = 0:

Oscillator divider 1 disabled

OD1EN = 1:

Oscillator divider 1 enabled

Reserved

14:5

0000000000

Reserved. Reads return 0. Writes have no effect.

OSCDIV1

4:0

R/W

00000

Divider OD1 ratio (CLKOUT3 divider)

OSCDIV1 = 00000:

Divide by 1

OSCDIV1 = 00001:

Divide by 2

OSCDIV1 = 00010:

Divide by 3

OSCDIV1 = 00011:

Divide by 4

OSCDIV1 = 00100:

Divide by 5

OSCDIV1 = 00101:

Divide by 6

OSCDIV1 = 00110:

Divide by 7

OSCDIV1 = 00111:

Divide by 8

OSCDIV1 = 01000:

Divide by 9

OSCDIV1 = 01001:

Divide by 10

OSCDIV1 = 01010:

Divide by 11

OSCDIV1 = 01011:

Divide by 12

OSCDIV1 = 01100:

Divide by 13

OSCDIV1 = 01101:

Divide by 14

OSCDIV1 = 01110:

Divide by 15

OSCDIV1 = 01111:

Divide by 16

OSCDIV1 = 10000:

Divide by 17

OSCDIV1 = 10001:

Divide by 18

OSCDIV1 = 10010:

Divide by 19

OSCDIV1 = 10011:

Divide by 20

OSCDIV1 = 10100:

Divide by 21

OSCDIV1 = 10101:

Divide by 22

OSCDIV1 = 10110:

Divide by 23

OSCDIV1 = 10111:

Divide by 24

OSCDIV1 = 11000:

Divide by 25

OSCDIV1 = 11001:

Divide by 26

OSCDIV1 = 11010:

Divide by 27

OSCDIV1 = 11011:

Divide by 28

OSCDIV1 = 11100:

Divide by 29

OSCDIV1 = 11101:

Divide by 30

OSCDIV1 = 11110:

Divide by 31

OSCDIV1 = 11111:

Divide by 32

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