CS7654 datasheet(8/62 Pages) CIRRUS

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CS7654

GENERAL DESCRIPTION

Overview

The CS7654 is a complete color space converter

and multi-standard digital video encoder imple-

mented in current CMOS technology. It provides

all necessary digital image processing for standard

four-color interline transfer CCD imagers. The

CS7654 processes the magenta, yellow, cyan, and

green (MYCG) CCD imager data into YCrCb for-

matted component and into NTSC-M, NTSC-J,

PAL-B, PAL-D, PAL-G, PAL-H, PAL-I, PAL-M,

PAL-N, or PAL-N Argentina-compatible analog

video.

Two 10-bit DAC outputs provide high quality S-

Video analog output while another 10-bit DAC si-

multaneously generates composite analog video.

In order to lower overall system costs, the CS7654

provides an internal voltage reference that elimi-

nates the requirement for an external, discrete,

three-pin voltage reference.

The CS7654 forms the heart of a four chip digital

CCD Camera. The four chips include the CCD im-

ager, the CS7615 CCD digitizer, the CS7654 color

space processor, and a vertical drive interface-chip

for the CCD imager. Most four-phase CCD imag-

ers (and their associated vertical drives) can be

used with the CS7615 digitizer and the CS7654

processor to form a simple and cost-effective Ana-

log output format digital camera. The CS7615 and

CS7654 together support imager formats ranging

from 175×175 pixels up to 1000x1000 pixels. Tim-

ing control is located in the CS7615 analog proces-

sor, while the CS7654 synchronizes itself by

decoding the timing cues embedded in the CS7615

data stream. Alternately, the CS7654 accepts hori-

zontal and vertical timing signals on HREFIN and

VREFIN pins. The block diagram in Figure 1 illus-

trates a typical system interconnect.

The CS7654 provides color separation of standard

MYCG chroma block data from industry standard

four-color CCD imagers. Gamma correction and

white balance adjustment functions are also includ-

ed in the CS7654. The YCrCb (luminance and

chrominance) data is output at twice the scaled

pixel rate in 10-bit format. The digital YCrCb out-

put data from the CS7654 conforms to the ITU-656

parallel component digital video recommendation

with embedded synchronization (see Embedded

EAV and SAV discussion).

The CS7654 incorporates an internal horizontal

scaler which may be turned on to increase the hor-

izontal pixel count of the popular 360 (CIF) and

512 horizontal pixel per line imagers. The most

common target resolutions for the scaler are 640

and 720 pixels per line (square and rectangular pix-

el formats), but it is possible to provide generic

scaling of M/N where M and N are values from 1 to

31.

The CS7615 and CS7654 chip set supports a wide

range of imager formats while providing an output

format that follows the ITU-601 Component Digi-

tal Video recommendation. The ITU-601 docu-

ment primarily specifies horizontal resolutions of

720 active horizontal pixels (which is required for

broadcast

television

compatibility).

However,

many of today’s digital video receivers are capable

of operating with a wide range of video image for-

mats. Even though these digital video receivers al-

low image formats not specified in the ITU-

601/656 recommendation, all of these receivers ex-

pect the basic ITU-601/656 protocol to be followed

in terms of data sequence and timing cues. This is

the case with the CS7654, where all output formats

CCD

Bias

Vertical

Drive

Timing

CDS/ADC

+18V to +12V

+5V

CS7654

512x480

CS7615

CCD

Image

Processor

I2C

Figure 1. Typical 4-Chip Digital CCD Camera

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