CS7654 datasheet(47/62 Pages) CIRRUS

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CS7654

Low Power Register (20h at SA 0x34h)

Setting bit PD to “1” will place the CS7654 in low power mode.

Test Enable Register (21h at SA 0x34h)

This register is reserved.

Reserved Register (22h at SA 0x34h)

This register is reserved and returns a valud of 00 when read.

Anti-Alias (23h at SA 0x34h)

This register is reserved and must be set to 08h for normal operation.

Test_AA2 (24h at SA 0x34h)

This register is reserved and must be set to FFh for normal operation

Test_AA3 (25h at SA 0x34h)

This register is reserved and must be set to FFh for normal operation

Test_AA4 (26h at SA 0x34h)

This register is reserved and must be set to FFh for normal operation

Flare Control 1 (27h at SA 0x34h)

Y_THR[9:2]

Flare control filter Y threshold bits 9-2 (MSB). (Bits 1 and 0 set to 0.)

Flare Control 2 (28h at SA 0x34h)

Cr_L

[9:2]

Flare control filter Cr low threshold bits 9-2 (MSB).

765

4321

res

Reserved

R/W

76543210

Y_THR9

Y_THR8

Y_THR7

Y_THR6

Y_THR5

Y_THR4

Y_THR3

Y_THR2

R/W

76543210

Cr_L9

Cr_L8

Cr_L7

Cr_L6

Cr_L5

Cr_L4

Cr_L3

Cr_L2

R/W

CS7654 数据表(PDF) 47 Page - Cirrus Logic

CS7654 数据表(HTML) 47 Page - Cirrus Logic

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CS7654 数据表(PDF) 47 Page - Cirrus Logic

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