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CS7654 数据表(PDF) 5 Page - Cirrus Logic |
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CS7654 数据表(HTML) 5 Page - Cirrus Logic |
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5 / 62 page ![]() CS7654 5 POWER CONSUMPTION (T A = 25 °C; VDD = 5 V; CL = no load; Input Levels: logic 0 = 0 V, logic 1 = VDD.) Notes: 1. Low-Z - 3 dacs on 2. Output current levels with ISET = 4 K Ω , VREF = 1.232 V. 3. DACs are set to low impedance mode 4. DACs are set to high impedance mode 5. Times for black-to-white-level and white-to-black-level transitions. Parameter Symbol Min Typ Max Unit Power Supply Supply Voltage VAA 4.75 5.0 5.25 V Digital Supply Current (Encoder) IAA1 - 70 mA Analog Supply (Encoder) Low-Z (Note 1) IAA2 - 100 - mA Power Supply Rejection Ratio PSRR - 0.02 0.05 %/% Normal Mode IDD -150 200 mA Low Power Mode IDD -7 16 mA Analog Outputs Full Scale Output Current COMP_VID/Y/C (Notes 2, 3) IO 32.9 34.7 36.5 mA Full Scale Output Current COMP_VID/Y/C (Notes 2, 4) IO 8.22 8.68 9.13 mA LSB Current COMP_VID/Y/C (Notes 2, 3) IB 32.2 33.9 35.7 mA LSB Current COMP_VID/Y/C (Notes 2, 4) IB 8.04 8.48 8.92 mA DAC-to DAC Matching MAT - 2 - % Output Compliance VOC 0 - + 1.4 V Output Impedance ROUT - 15 - k Ω Output Capacitance COUT - - 30 pF DAC Output Delay ODEL - 4 12 nsec DAC Rise/Fall Time (Note 5) TRF - 2.5 5 nsec CLKIN2X CLKIN Mosaic Input Data DI[9:0] tH2 tS2 tH1 tS1 CLKOUT Output Data DOA[9:0] DOB[9:0] tPD t OH Input Timing Diagram Output Timing Diagram |
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