CS7654 datasheet(29/62 Pages) CIRRUS

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CS7654

Reserved Registers and Test Pins

To ensure proper operation of the CS7654, connect

and SCENABLE (pin 45) to ground, and connect

TEST1 (pin 64) and TEST2 (pin 42) to VDD. Reg-

isters 23h - 26h at SA 0x34h must be set to a value

of FFh after reset. All other reserved registers may

be left in their default states.

General Purpose I/O Port

The CS7654 has a GPIO port and register that is

available when the device is configured for I2C host

interface operation. The GPIO [2:0] pins operate as

input or outputs pins for the GPIO_DATA_REG

are configured for input operation when the corre-

sponding GPIO_CTRL_REG [2:0] bits are set to 0

and output when set to 1. In GPIO input mode, the

CS7654 will latch the data on the [2:0] pins into the

corresponding bit locations of GPIO_DATA_REG

when it detects register address 0×0A at SA 0x00h

through the I2C interface. A detection of address

0×0A can happen in two ways. The first and most

common way this will happen is when address

0×0A is written to the CS7654 via its I2C interface.

The second method for detecting address 0×0A is

implemented by accessing register address 0×09 at

SA 0x00h through I2C. In I2C host interface opera-

tion, the CS7654 register address pointer will auto-

increment to address 0×0A after an address 0×09

access ( at SA 0x00h ).

CS7654 station address[7] +W

1Ah (addrs of low byte Count)

count value

CS7654 station address[7] +W

1Bh (addrs of high byte Count)

count value

Dest. station address + W

Dest. device address

data value

Dest. station address + W

EPROM Block 000 (binary)

Address 00h

Figure 17. Map of EPROM table for initialization

of registers

CS7654 station address[7] +W

0Ch (gamma reg. addrs)

data = select RGB ram

data [gamma loc 00h]

data [gamma loc 01h]

data [gamma loc FFh]

Figure 18. Map of EPROM table for storing

gamma ram initialization data.

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