CS7654 datasheet(31/62 Pages) CIRRUS

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CS7654

Chrominance DAC

The SVID_C pin is driven from a 10-bit 27 MHz

current output DAC that internally receives the

SVID_C or chrominance portion of the video sig-

nal (color only). SVID_C is designed to drive prop-

er video levels into a 37.5

Ω load. Reference the

detailed electrical section of this data sheet for the

exact SVID_C digital to analog AC and DC perfor-

mance data. A EN_C enable control register bit in

the Control Register 1 (0×05 at SA 0x00h) is pro-

vided to enable or disable the chrominance DAC.

For a complete disable and lower power operation

the chrominance DAC can be totally shut down via

the SVIDCHR_PD register bit in the Control Reg-

ister 4 (0×04 at SA 0x00h). In this mode turn-on

through the control register will not be instanta-

neous.

COMP_VID DAC

The COMP_VID pin is driven from a 10-bit

27 MHz current output DAC that internally re-

ceives a combined luma and chroma signal to pro-

vide composite video output. COMP_VID is

designed to drive proper composite video levels

into a 37.5

Ω load. Reference the detailed electrical

section of this data sheet for the exact COMP_VID

digital to analog ac and dc performance data. The

EN_COM enable control register bit, in Control

able or disable the output pin. When disabled, there

is no current flow from the output. For a complete

disable

and

lower

power

operation,

the

COMP_VID DAC can be totally shut down via the

COMDAC_PD control register bit in Control

on through the control register will not be instanta-

neous.

Depending on the external resistor connected to the

ISET_DAC pin the output drive of the DACs can

be changed. There are two modes in which the

DACs should either be operated in. An external re-

sistor of 4 k

Ω must be connected to the ISET_DAC

pin.

The first mode is the high impedance mode

(LOW_IMP bit set to 0). The DAC outputs will

then drive a double terminated load of 300

Ω and

will output a video signal which conforms to the

analog video specifications for NTSC and PAL.

External buffers will be needed if the DAC output

load differs from 300

Ω.

The second mode is the low impedence mode

(LOW_IMP but set to 1). The DAC output will

then drive a double terminated load of 75

Ω and

will output a video signal which conforms to the

analog video specifications for NTSC and PAL. No

external buffers are necessary, the ouputs can di-

rectly drive a television input.

Note If some of the 3 DACs are not used, it is

strongly recommended to power them down (see

CONTROL_4 register) in order to reduce the pow-

er dissipation.

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