5228-DS07-R datasheet(25/100 Pages) BOARDCOM

25 / 100 page

Data Sheet

BCM5228

7/12/04

Broa d c om Co rp o r a t i o n

Document

5228-DS09-405-R

Hardware Signal Definition Table

Page 13

H02

MASTERPHY/

SFRAME

I/OPD

Master PHY Address Mode. Active high.

This forces PHY address 0 to be a global write

address for all PHYs within the BCM5228. An

active high during power-on reset selects the

master PHY address mode, while an active

low or being left unconnected selects the

normal address mode.

Serial LED Frame. After power-on reset, this

pin sources the serial LED frame output signal

if serial LED mode is enabled.

Mode

C16

157

RESET#

IPU

Reset. Active Low. Resets the BCM5228. Pin

not included in NAND chain.

N15

109

F100

IPU

10/100 Mode Select. When high and ANEN is

low, all transceivers are forced to 100BASE-X

operation. When low and ANEN is low, all

transceivers are forced to 10BASE-T

operation. When ANEN is high, F100 has no

effect on the operation.

M13

108

ANEN

IPU

Auto-Negotiation Enable. Active high. When

pulled high, auto-negotiation begins

immediately after reset. When low, auto-

negotiation is disabled after reset. Auto-

negotiation can be enabled under software

control (register 0, bit 12) if auto-negotiation is

enabled through hardware.

C15

156

FDXEN

IPD

Full-Duplex Mode Enable. The FDXEN pin is

logically ORed with an MII control bit to

generate an internal full-duplex enable signal.

When FDXEN is high, the BCM5228 can

operate in full-duplex mode as determined by

auto-negotiation. When FDXEN is low, the

internal control bit (register 0, bit 8)

determines the full-duplex operating mode.

Initial value of the internal control bit is zero.

G01

TXER_EN

I/OPU

TXER Enable. Active high. When pulled high

during power-on reset, TXER[1:8]/LED1[1:8]

pins become TXER[1:8] input. Otherwise they

become LED1[1:8] output.

F05

MDIX_DIS

I/OPD

HP Auto-MDIX Disable. Active high. When

pulled high during reset, automatic TX cable

swap detection function of the BCM5228 is

disabled. Leave this pin unconnected for

normal operation.

F04

TESTEN

IPD

Test Enable. Active high test control input

used along with PHYAD[4:0] to select the

NAND-chain test mode. This test mode is

latched when TESTEN is pulsed high, then

low, with PHYAD[4:0]=10111. This pin is not

included in the NAND chain and must be

pulled low or left unconnected during normal

operation.

Table 2: Pin Definitions (Cont.)

BCM5228B BCM5228F BCM5228U Pin Label

I/O

Description

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