5228-DS07-R datasheet(41/100 Pages) BOARDCOM

41 / 100 page

Data Sheet

BCM5228

7/12/04

Broa d c om Co rp o r a t i o n

Document

5228-DS09-405-R

LED Modes

Page 29

Section 5: LED Mode s

DESCRIPTION

The BCM5228 offers a rich set of LED display outputs through serial and parallel LED modes. There are two serial LED

modes available, Serial LED mode and Low-Cost Serial LED mode. The serial LED mode provides compatibility with few

other Broadcom PHYs. Serial LED modes are selected by hardware only during power-on reset. When any serial LED mode

is enabled global hardware interrupt feature is not available. However, if interrupt and a serial or a Low-Cost Serial LED

mode is desired simultaneously, then a parallel LED can be programmed to provide on interrupt output per port and eight

such interrupt can be ORed to obtain a global interrupt.

SERIAL LED MODE

The Serial LED mode is enabled only by having the SER_EN pin high and the LC_SER_EN pin low during power-on reset.

If Serial LED mode is enabled, then the Low-cost Serial LED mode and hardware global interrupt are disabled. In Serial LED

mode, the BCM5228 sources a serial data stream, the associated clock, and a framing signal as follows:

•

Serial data stream, SLED_DO, which is an active low bit stream containing 48 bits per frame.

•

Serial data clock, SLED_CLK, is used to clock out SLED_DO on the falling edge of this clock. SLED-DO is valid on the

rising edge of this clock. SLED_CLK is approximately 3.125 MHz in forced 100BASE-T and -FX modes, and 2.5 MHz in

all other modes.

•

Framing pulse, SFRAME, which is a logic high pulse occurring once every 48 SLED_DO bit times. SFRAME goes high

coincident with bit 0 of port 1.

When the serial LED mode is enabled by hardware, the LED stream is selected for SLED_DO as shown in Table 6,

depending on the values of bits 14 and 15 of MII register 1Ah. The data stream contains bit 0 to bit 5 for port 1, bit 0 to bit 5

for port 2, … and bit 0 to bit 5 for port 8.

NOTE—A global interrupt indicates an interrupt from any of the eight PHYs as if they were ORed together. A port interrupt

is provided on a per-PHY basis.

Table 6: Serial LED Mode Bit Framing

Reg 1Ah

Serial Bit 5 Serial Bit 4

Serial Bit 3

Serial Bit 2

Serial Bit 1

Serial Bit 0

Bit 15 = 0

Bit 14 = 0

FDX

COL

Speed100

Link

Transmit

Receive

Bit 15 = 0

Bit 14 = 1

FDX

Global Interrupt

Speed100

Link

Port Interrupt

Activity

Bit 15 = 1

Bit 14 = 0

FDX

COL

Speed100

Link

FDX

Activity

Bit 15 = 1

Bit 14 = 1

FDX

Global Interrupt

Speed100

Link

FDX

Activity

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