5228-DS07-R datasheet(15/100 Pages) BOARDCOM

15 / 100 page

Data Sheet

BCM5228

7/12/04

Broa d c om Co rp o r a t i o n

Document

5228-DS09-405-R

Auto-Negotiation

Page 3

AUTO-NEGOTIATION

The BCM5228 contains the ability to negotiate its mode of operation over the twisted-pair link using the auto-negotiation

mechanism defined in the IEEE 802.3u specification. Auto-negotiation can be enabled or disabled by hardware or software

control. When the auto-negotiation function is enabled, the BCM5228 automatically chooses its mode of operation by

advertising its abilities and comparing them with those received from its link partner. The BCM5228 can be configured to

advertise 100BASE-TX full-duplex and/or half-duplex and 10BASE-T full-duplex and/or half-duplex. Each transceiver

negotiates independently with its link partner and chooses the highest level of operation available for its own link.

DIGITAL ADAPTIVE EQUALIZER

The digital adaptive equalizer removes interzonal interference created by the transmission channel media. The equalizer

accepts sampled unequalized data from the ADC on each channel and produces equalized data. The BCM5228 achieves

an optimum signal to noise ratio by using a combination of feed-forward equalization and decision-feedback equalization.

This powerful technique achieves a 100BASE-TX BER of less than 1 x 10-12 for transmission up to 100 meters on Category 5

twisted-pair cable, even in harsh noise environments. The digital adaptive equalizers in the BCM5228 achieve performance

close to theoretical limits. The all-digital nature of the design makes the performance very tolerant to on-chip noise. The filter

coefficients are self adapting to any quality of cable or cable length. Because of transmit pre-equalization in 10BASE-T mode

and complete lack of ISI in 100BASE-FX mode, the adaptive equalizer is bypassed in this mode of operation.

ADC

Each receive channel has its own 125-MHz analog to digital converter (ADC). The ADC samples the incoming data on the

receive channel and produces a digital output. The output of the ADC is fed to the digital adaptive equalizer. Advanced

analog circuit techniques achieve low offset, high power supply noise rejection, fast settling time, and low bit error rate (BER).

DIGITAL CLOCK RECOVERY/GENERATOR

The all-digital clock recovery and generator block creates all internal transmit and receive clocks. The transmit clocks are

locked to the 50-MHz clock input, while the receive clocks are locked to the incoming data streams. Clock recovery circuits

optimized to MLT3, NRZI, and Manchester encoding schemes are included for use with each of the three different operating

modes. The input data streams are sampled by the recovered clock from each port and fed synchronously to the respective

digital adaptive equalizer.

BASELINE WANDER CORRECTION

A 100BASE-TX data stream is not always DC balanced. Because the receive signal must pass through a transformer, the

DC offset of the differential receive input can wander. This effect, known as baseline wander, can greatly reduce the noise

immunity of the receiver. The BCM5228 automatically compensates for baseline wander by removing the DC offset from the

5228-DS07-R 数据表(PDF) 15 Page - Broadcom Corporation.

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