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5228-DS07-R 数据表(PDF) 19 Page - Broadcom Corporation. |
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5228-DS07-R 数据表(HTML) 19 Page - Broadcom Corporation. |
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19 / 100 page ![]() Data Sheet BCM5228 7/12/04 Broa d c om Co rp o r a t i o n Document 5228-DS09-405-R Interrupt Mode Page 7 Transmit data and control information are passed from the MAC to the PHY in 10 bit frames, as in the receive path. In 100 Mbps mode, each frame represents a new byte of data. In 10 Mbps mode, each byte of data is repeated 10 times, and the PHY can transmit any one of every 10 frames. INTERRUPT MODE The BCM5228 can be programmed to provide an interrupt output consisting of an OR of the eight interrupts, one from each PHY. The interrupt feature is disabled by default. The interrupt capability is enabled by setting MII register 1Ah, bit 14. The SLED_DO pin becomes the INTR# pin, when the SERIAL_EN is pulled low during power-up reset. If a serial LED mode is required, hardware interrupt can be obtained by wire ORing LED2{1:8} open drain outputs and programming LED2 to output interrupt by setting TXER/LED1{5:3} pins to a 5 during power-on reset. The status of each interrupt source is also reflected in register 1Ah, bits 1, 2 and 3. The sources of interrupt are change in link, speed or full-duplex status. If any type of interrupt occurs, the Interrupt Status bit, register 1Ah, bit 0 is set. In addition, each transceiver has its own register controlling the interrupt function. If the interrupt enable bit is set to 0, no status bits sets, and no interrupts are generated. If the interrupt enable bit is set to 1, the following conditions apply: • If mask status bits are to 0 and the interrupt mask is set to 1, status bits are set but no interrupts are generated. • If mask status bits are set to 0 and the interrupt mask is set to 0, status bits and interrupts are available. • If mask status bits are set to 1 and the interrupt mask is set to 0, no status bits and no interrupts are available. Changes from active to inactive or vice versa causes an interrupt. Setting register 1Ah, bit 8 high masks all interrupts, regardless of the settings of the individual mask bits. |
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