5228-DS07-R datasheet(47/100 Pages) BOARDCOM

47 / 100 page

Data Sheet

BCM5228

7/12/04

Broa d c om Co rp o r a t i o n

Document

5228-DS09-405-R

Page 35

Sec t i on 6: Re gi st er Su mm a r y

MII MANAGEMENT INTERFACE: REGISTER PROGRAMMING

The BCM5228 fully complies with the IEEE 802.3u Media Independent Interface (MII) specification. The MII management

interface registers of each port are serially written-to and read from using a common set of MDIO and MDC pins. A single

clock waveform must be provided to the BCM5228 at a rate of 0–25 MHz through the MDC pin. The serial data is

communicated on the MDIO pin. Every MDIO bit must have the same period as the MDC clock. The MDIO bits are latched

on the rising edge of the MDC clock. Every MII read or write instruction frame contains the following fields:

Preamble (PRE). Thirty-two consecutive 1 bits must be sent through the MDIO pin to the BCM5228 to signal the beginning

of an RMII instruction. Fewer than thirty-two 1 bits causes the remainder of the instruction to be ignored.

Start of Frame (ST). A 01 pattern indicates that the start of the instruction follows.

Operation Code (OP). A Read instruction is indicated by 10, while a Write instruction is indicated by 01.

PHY Address (PHYAD). A 5-bit PHY address follows next, with the MSB transmitted first. The PHY address allows a single

MDIO bus to access multiple PHY chips. The BCM5228 supports a complete address space with PHYAD[4:0] input-pins

used as the base address for selecting one of the eight transceivers.

BCM5228, containing register addresses and bit definitions, are provided on the following pages.

Turnaround (TA). The next two bit times are used to avoid contention on the MDIO pin when a Read operation is performed.

For a Write operation, 10 must be sent to the BCM5228 chip during these two bit times. For a Read operation, the MDIO pin

must be placed into High-Impedance during these two bit times. The chip drives the MDIO pin to 0 during the second bit time.

Data. The last 16 bits of the frame are the actual data bits. For a Write operation, these bits are sent to the BCM5228,

whereas, for a read operation, these bits are driven by the BCM5228. In either case, the MSB is transmitted first. When

writing to the BCM5228, the data field bits must be stable 10 ns before the rising edge of MDC, and must be held valid for

10 ns after the rising edge of MDC. When reading from the BCM5228, the data field bits are valid after the rising-edge of

MDC until the next rising edge of MDC.

Idle. A high impedance state of the MDIO line. All tri-state drivers are disabled and the PHY’s pull-up resistor pulls the MDIO

line to logic 1.

Table 16: MII Management Frame Format

Operation

PRE

PHYAD

REGAD

Data

Idle

Direction

Read

1 ... 1

AAAAA

RRRRR

Z ... Z

D ... D

Driven to BCM5228

Driven by BCM5228

Write

1 ... 1

AAAAA

RRRRR

D ... D

Driven to BCM5228

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