5228-DS07-R datasheet(75/100 Pages) BOARDCOM

75 / 100 page

Data Sheet

BCM5228

7/12/04

Broa d c om Co rp o r a t i o n

Document

5228-DS09-405-R

Auxiliary Mode 4 (PHY 1) Register (Shadow Register)

Page 63

AUXILIARY MODE 4 (PHY 1) REGISTER (SHADOW REGISTER)

MII LED Select Enable. Enables configuration of LED functions through MII register writes when this bit is set to a 1.

Otherwise, power-on reset configurations are in effect.

Parallel LED3 Select[1:0]. Bit 7 and 6 select LED output for the parallel LED3 pin if MII LED select enable is set to a 1.

Parallel LED2 Select[2:0]. Bit 5 and 3 select LED output for the parallel LED2 pin if MII LED select enable is set to a 1.

Parallel LED1 Select[2:0]. Bit 2 and 0 select LED output for the parallel LED1 pin if MII LED select enable is set to a 1.

Table 40: Auxiliary Mode 4 (PHY 1) Register (Shadow Register 26d, 1Ah)

BIt

Name

R/W

Description

Default

15:9

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

–

0011 000b

MII LED Select Enable

R/W

1 = Enable LED output selection through MII

7:6

Parallel LED3 Select[1:0]

R/W

Configuration bits for LED3 output. For details, see

“LED Modes” on page 29.

TXER/LED1[7:6]b

b. Status of TXER/LED1[7:0] during power-on reset determines the default values for parallel LED3, LED2 and LED1 selects.

5:3

Parallel LED2 Select[2:0]

R/W

Configuration bits for LED2 output. For details, see

“LED Modes” on page 29.

TXER/LED1[5:3]

2:0

Parallel LED1 Select[2:0]

R/W

Configuration bits for LED1 output. For details, see

“LED Modes” on page 29.

TXER/LED1[2:0]

Note: R/W = Read/Write, RO = Read Only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation. MII Shadow register bank 1 is accessed by setting MII register 1Fh bit 7 to a 1.

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