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5228-DS07-R 数据表(PDF) 11 Page - Broadcom Corporation. |
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5228-DS07-R 数据表(HTML) 11 Page - Broadcom Corporation. |
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11 / 100 page ![]() Data Sheet BCM5228 7/12/04 Broa d c om Co rp o r a t i o n Document 5228-DS09-405-R Page xi LIST OF TABLES Table 1: 4B5B Encoding..................................................................................................................................... 4 Table 2: Pin Definitions....................................................................................................................................... 9 Table 3: BGA Ballout by Signal Name.............................................................................................................. 22 Table 4: Receive FIFO Size Select .................................................................................................................. 27 Table 5: Jumbo Packet Enable and Descrambler Lock Timer .........................................................................27 Table 6: Serial LED Mode Bit Framing ............................................................................................................. 29 Table 7: Low-Cost Serial Mode Bank 1 LED Selection .................................................................................... 30 Table 8: Low-Cost Serial Mode Bank 2 LED Selection .................................................................................... 30 Table 9: Low-Cost Serial Mode Bank 3 LED Selection .................................................................................... 31 Table 10: Low-Cost Serial Mode Bank 4 LED Selection .................................................................................. 31 Table 11: Low-Cost Serial Mode Bank 5 LED Selection .................................................................................. 31 Table 12: Low-Cost Serial Mode Bank 6 LED Selection .................................................................................. 32 Table 13: Parallel LED Mode LED1 Selection .................................................................................................. 33 Table 14: Parallel LED Mode LED2 Selection .................................................................................................. 33 Table 15: Parallel LED Mode LED3 Selection .................................................................................................. 34 Table 16: MII Management Frame Format....................................................................................................... 35 Table 17: MII Register Map Summary.............................................................................................................. 37 Table 18: MII Shadow Register Map Summary (MII Register 1Fh, bit7 = 1) .................................................... 38 Table 19: MII Control Register (Address 00d, 00h) .......................................................................................... 39 Table 20: MII Status Register (Address 01d, 01h) ........................................................................................... 41 Table 21: PHY Identifier Registers (Addresses 02d and 03d, 02h and 03h).................................................... 42 Table 22: Auto-Negotiation Advertisement Register (Address 04d, 04h)......................................................... 43 Table 23: Auto-Negotiation Link Partner Ability Register (Address 05d, 05h) .................................................. 44 Table 24: Auto-Negotiation Expansion Register (Address 06d, 06h) ............................................................... 45 Table 25: Next Page Transmit Register (Address 07d, 07h)............................................................................ 46 Table 26: Next Page Transmit Register (Address 08d, 08h)............................................................................ 47 Table 27: 100-BASE-X Auxiliary Control Register (Address 16d, 10h) ............................................................ 48 Table 28: 100BASE-X Auxiliary Status Register (Address 17d, 11h)............................................................... 49 Table 29: 100BASE-X Receive Error Counter (Address 18d, 12h) .................................................................. 50 Table 30: 100BASE-X False Carrier Sense Counter (Address 19d, 13h) ........................................................ 51 Table 31: 100BASE-X Disconnect Counter...................................................................................................... 51 Table 32: Auxiliary Control/Status Register (Address 24d, 18h) ...................................................................... 52 |
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