5228-DS07-R datasheet(39/100 Pages) BOARDCOM

39 / 100 page

Data Sheet

BCM5228

7/12/04

Broa d c om Co rp o r a t i o n

Document

5228-DS09-405-R

Jumbo Packet Mode

Page 27

JUMBO PACKET MODE

In 100BASE-X mode, the BCM5228 can support jumbo packet size. The size of the packet that can be handled reliably

depends on the descrambler lock timer settings and the receive FIFO size. By default, the BCM5228 provides an effective

10 bits of receive FIFO to allow for extremely large packet sizes. These modes are enabled by setting appropriate bits in the

MII registers. Table 4 shows the number of effective FIFO bits supported.

When changing the receive FIFO size, it is necessary to identify the receive packet size requirement and set the descrambler

timer lock accordingly. The descrambler lock is controlled by the Jumbo Packet Enable bit located in register 1HBh, bit 10.

The packet size that can be reliably received is the lower number indicated by two settings: the Jumbo Packet Enable bit

and the two Extended FIFO Enable bits.

PHY ADDRESS

Each transceiver in the BCM5228 has a unique PHY address for MII management. The PHY address is determined by the

using the base address, which is input on the PHYAD[4:0] pins. The following shows the addressing of the eight PHYs.

PHY0 = PHYAD + 0, PHY1 = PHYAD + 1,... PHY7 = PHYAD + 7

Every time an MII write or read operation is executed, the transceiver compares the PHY address with its own PHY address

definition. The operation is executed only when the addresses match.

Table 4: Receive FIFO Size Select

Jumbo Packet FIFO Enable

Reg 1Bh bit 9

Extended FIFO Enable

Reg 10h bit 2

Number of Effective

FIFO Bits Supported

Packet Size

(bytesb)

b. The packet size calculation is based on 50 ppm clock tolerance for local and link partner.

12 500

25 000

40 (20a)

a. In this mode, the BCM5228 operation is guaranteed to only 20 bits of effective FIFO depth, although under some

circumstances, it could behave as if the FIFO depth is 40 bits.

50 000/25 000

Table 5: Jumbo Packet Enable and Descrambler Lock Timer

Jumbo Packet Enable

Reg 1Bh bit 10

Descrambler Lock Timer

Packet Size

720

µs

9050

5792

µs

72 400

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