Production Specification

07/03/02

B roa dcom Co rpo rat ion

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5802-DS03-405-R

The following table shows alignment requirements for all memory-resident data in IPsec crypto/authentication operations.

The flexibility with respect to input packet payload data allows extreme combinations to be supported. For instance, a packet

with 16,000 bytes of input payload data could be described as a chain of 16,000 descriptors, with each descriptor holding

performance from the huge number of descriptor fetches.

The following table shows alignment requirements for all memory-resident data in DH/RSA/DSA operations.

Because IKE/SSL/TLS key setups operate at or above Layer 4 of the network stack, users have full control of the data

memory allocation. Aligning data at the 32-bit boundary is relatively easy to do for software.

Table 24:

Memory-Resident Data Alignment Requirements in IPsec Crypto/Authentication Operations

Memory-Resident Data Type

Alignment Requirement, Size Requirement

Packet Payload Data

Packet Input Data Buffers (per descriptor)

None (byte), None (byte)

Packet Output Data Buffers (per descriptor)

32-bit, length multiple of 32 bits

Control and Command Structures

Descriptors (Input and Output)

32-bit, fixed size (3 words of 32 bits)

Command Context Structure

32-bit, fixed size (19 words of 32 bits)

Master Command Record

32-bit, variable size (1 + #pkts*8 32-bit words)

Table 25:

Memory-Resident Data Alignment Requirements in DH/RSA/DSA Operations

Memory-Resident Data Type

Alignment Requirement, Size Requirement

Packet Payload Data

Input Data Buffers (per descriptor)

32-bit, length multiple of 32 bits

Output Data Buffers (per descriptor)

32-bit, length multiple of 32 bits

Control and Command Structures

Descriptors (Input and Output)

32-bit, fixed size (3 words of 32 bits)

Command Context Structure

32-bit, fixed size (variable words of 32 bits)

Master Command Record

32-bit, variable size (1 + #key setup*8 32-bit words)