5802-DS02-R datasheet(18/50 Pages) BOARDCOM

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■ BCM5802

Production Specification

07/03/02

B roa dcom Co rpo rat ion

Page 10 Hardware Signal Definition Table

Document

5802-DS03-405-R

AD[0]

80 PCI multiplexed address/data bus.

PCI_CLK

8 PCI clock, 25-33 MHz.

GNT#

17 PCI bus grant allowing the chip to use the bus.

FRAME#

45 PCI frame, indicates the beginning and duration of a master transfer.

IRDY#

46 PCI initiator ready.

TRDY#

47 PCI target ready.

DEVSEL#

49 PCI device select, asserted by an access target.

STOP#

50 PCI stop, requesting that the current master stop an active transfer.

PERR#

53 PCI parity error.

SERR#

54 PCI system error, open drain.

PAR

55 PCI parity.

REQ#

19 PCI bus request.

RESET#

16 PCI reset, tri-states all PCI outputs.

INT#

15 PCI interrupt output, open drain.

IDSEL

32 PCI Initialization Device Request, used for PCI configuration cycles.

CBE#[3]

31 PCI command/byte enable, provides PCI bus command and data byte enables.

CBE#[2]

43 PCI command/byte enable, provides PCI bus command and data byte enables.

CBE#[1]

58 PCI command/byte enable, provides PCI bus command and data byte enables.

CBE#[0]

70 PCI command/byte enable, provides PCI bus command and data byte enables.

VCC

51 Must be pulled up to VCC (PCI LOCK_).

VCC

Power pins, must be connected to a 3.3V source: 10, 18, 26, 40, 48, 57, 61, 74, 81, 90, 92, 93, 102, 103,

109, 110, 126, 127, 133, 134, 135, 143, 144.

GND

Ground pins: 5, 12, 14, 22, 30, 34, 44, 52, 56, 64, 69, 78, 84, 85, 89, 99, 100, 106, 107, 108, 116, 117,

118, 119, 122, 123, 136, 137, 139, 140.

AVCC1

94 Analog VCC for 4x PLL. Connect to 3.3V.

AGND1

98 Analog ground for 4x PLL.

AVCC2

9 Analog VCC for deskew PLL. Connect to 3.3V.

AGND2

7 Analog ground for deskew PLL.

VIO

111 PCI clamp voltage bias. Connect to 3.3V for 3.3V signaling environments. Connect to 5V

for 5V signaling environments.

EXPORT

138 EXPORT pin (high = 56-bit encryption; low = strong encryption). Internally pulled up.

TEST

1 Test pin, internally pulled down, should be grounded for regular operation. When TEST is

high, all outputs are tri-stated.

TRST#

131 Internally pulled up. Should be connected to ground for normal operation. Used for

boundary scan JTAG testing.

TMS

120 Test mode select for JTAG boundary scan. Internally pulled up. Should be connected to

VCC for normal operation.

TCK

6 Test mode clock for JTAG boundary scan. Internally pulled up. Unused in normal

operation; connect to either high or low static level.

Table 3:

PCI Interface Pin Definitions

Name

I/O

Pin # Description

5802-DS02-R 数据表(PDF) 18 Page - Broadcom Corporation.

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