Production Specification

07/03/02

B roa dcom Co rpo rat ion

In-System Performance Analysis

Document

5802-DS03-405-R

pre-fetches and writes back descriptors, command buffers, context parameters and packet data. This aggressive pre-fetch

enables the chip to run encryption and authentication engines at their full potential despite system latencies. Standard

shared PCI bus implementations that run at 20-33 MHz with per-access latencies in the range of 1 ms to 1.5 ms enable the

33 MHz, which is the high end of the core clock frequency, in systems where maximal performance is desired. The chip core

clock can be either directly copied from the PCI clock for reduced system cost, or generated asynchronously via an external

oscillator for maximal performance.

The values shown in the following table indicate outbound packet Mbps performance for 3DES, HMAC-SHA1, with new the

Security Association per packet.

Table 2:

Performance Table (Mbits/second)

PCI Clock Frequency

Packet Sizes (Bytes)

64

256

512

1024

2048

33 MHz

28

67

89

104

113