5802-DS02-R datasheet(7/50 Pages) BOARDCOM

7 / 50 page

■ BCM5802

Production Specification

07/03/02

B roa dcom Co rpo rat ion

Page vii

Document 5802-DS03-405-R

LIST OF TABLES

Table 1: BCM5802 Key Features and Statistics................................................................................................ 1

Table 2: Performance Table (Mbits/second) ..................................................................................................... 8

Table 3: PCI Interface Pin Definitions................................................................................................................ 9

Table 4: Data Buffer Chain Entries.................................................................................................................. 19

Table 5: Master Command Record ................................................................................................................. 20

Table 6: Packet Context Buffer........................................................................................................................ 21

Table 7: Data Buffer Chain Entries.................................................................................................................. 22

Table 8: Master Command Record ................................................................................................................. 23

Table 9: Diffie-Hellman Public Key Generation (X = gx mod N) Command Context ....................................... 24

Table 10: Diffie-Hellman Shared Secret Generation (K=Yx mod N) Command Context................................... 24

Table 11: RSA Public Key Command Context .................................................................................................. 25

Table 12: RSA Private Key Command Context................................................................................................. 25

Table 13: DSA Signing Command Context ....................................................................................................... 26

Table 14: DSA Verification Command Context ................................................................................................. 27

Table 15: RNG Direct Test Command Context ................................................................................................. 27

Table 16: RNG-SHA1 Test Command Context ................................................................................................. 27

Table 17: ModAdd Command Context (C = (A+B) mod N) ...............................................................................28

Table 18: ModSub Command Context (C = (A-B) mod N) ................................................................................ 28

Table 19: ModMul Command Context (C = A*B mod N) ................................................................................... 28

Table 20: ModRem Command Context (C = M mod N) .................................................................................... 29

Table 21: ModExp Command Context (C = ME mod N).................................................................................... 29

Table 22: ModInv Command Context (C = M-1 mod N = MN-2 mod N) ............................................................. 29

Table 23: MCR Input/Output Data Buffer Chaining ........................................................................................... 31

Table 24: Memory-Resident Data Alignment Requirements in IPsec Crypto/Authentication Operations ......... 32

Table 25: Memory-Resident Data Alignment Requirements in DH/RSA/DSA Operations................................ 32

Table 26: PCI 2.2-Compliant Configuration Space Registers ........................................................................... 34

Table 27: PCI Configuration Registers .............................................................................................................. 35

Table 28: PCI Memory BAR0 Space DMA Registers........................................................................................ 37

Table 29: DMA Control and Status Registers.................................................................................................... 37

Table 30: Electrical and Timing Specifications .................................................................................................. 39

Table 31: PCI Pin DC Specifications ................................................................................................................. 39

Table 32: 144-Pin DQFP Package Dimensions ................................................................................................ 41

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