5802-DS02-R datasheet(15/50 Pages) BOARDCOM

15 / 50 page

Production Specification

■ BCM5802

07/03/02

B roa dcom Co rpo rat ion

Document

5802-DS03-405-R

Hardware Interface

Page 7

The BCM5802 enables very low-cost PCI-based cards that can accelerate IPsec processing up to T3 rate. The following

figure shows the architecture of a BCM5802-based accelerator card. The accelerator card also provides key setup

acceleration on the chip as well as a hardware random number generator to generate secret keys.

HARDWARE INTERFACE

The only interface to the BCM5802 is a 32-bit PCI 2.2-compliant bus and a clock input. The following sections describe the

key features of the hardware interface.

Support for Both PCI 3.3V and PCI 5V Signaling Environments

Single supply voltage of 3.3V

±5%. Because I/O pins for the BCM5802 are 5V tolerant, the BCM5802 can be used in both

PCI 3.3V and PCI 5V environments.

Latency Tolerant Design

Descriptor for command as well as data buffers are pre-fetched to reduce the impact of PCI arbitration and system latency

upon overall performance. Large burst sizes (up to a maximum of 64 bytes) are used when possible to fetch descriptor,

command and packet payload data. Command context data is pre-fetched. Payload data is also pre-fetched and written back

in posted fashion.

Support for PCI Clock Rates from 25-33 MHz

PCI clock rates from 25-33 MHz are supported. In general, lower clock rates and higher PCI system latencies have little

impact on system performance, owing to aggressive data pre-fetch.

Figure 3:

PCI IPsec Accelerator Board - Architecture Concept

CPU

PCI Bus

Bridge

Memory

PCI

Mother Board

BCM5802

Cryptographic

Processor

BCM5802

Cryptographic

Processor

PCI

Add-In Card

LAN Interface

5802-DS02-R 数据表(PDF) 15 Page - Broadcom Corporation.

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