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5802-DS02-R 数据表(PDF) 44 Page - Broadcom Corporation. |
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5802-DS02-R 数据表(HTML) 44 Page - Broadcom Corporation. |
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44 / 50 page ![]() ■ BCM5802 Production Specification 07/03/02 B roa dcom Co rpo rat ion Page 36 BCM5802 Registers Document 5802-DS03-405-R PCI Class Code Register: 0x08 31:8 RO 0B4000 Class code value (hard-wired). 0x0B4000 (processor class, coprocessor subclass). PCI BIST Register, Cache line, Master Latency, Header: 0x0C 31 RO 0 BIST capable. The BCM5802 is not capable of performing PCI configuration BIST operation. 30 RW 0 BIST Start. Not supported on BCM5802. 29:28 RO 0 Reserved. 27:24 RO 0 BIST completion code. Not supported on BCM5802. 23:16 RW 0 Header type. 15:0 RW 0 Master latency timer. 7:0 RW 0 Cache line size. PCI Memory BAR: 0x10 31:0 RW 0xFFFF0000 Memory Base Address Register, 64 KB region, non-prefetchable, relocate in 32-bit space only. PCI MAX_LAT, MIN_GNT, Interrupt: 0x3C 31:24 RO 0 PCI MAX_LAT parameter. 23:16 RO 0 Length of burst period MIN_GNT. 15:8 RO 0x1 Interrupt pin register. 7:0 RW 0 Interrupt line register. PCI Retry Timeout, TRDY Timeout: 0x40 15:8 RW 0x80 Number of retries that the PCI interface performs. 7:0 RW 0x80 TRDY timeout value. Table 27: PCI Configuration Registers (Cont.) Bits Access Reset Purpose |
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