5802-DS02-R datasheet(45/50 Pages) BOARDCOM

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Production Specification

■ BCM5802

07/03/02

B roa dcom Co rpo rat ion

Document

5802-DS03-405-R

BCM5802 Registers

Page 37

DMA CONTROL AND STATUS REGISTERS

The DMA registers control how master command structures, packet context and packet data are fetched and then stored

after processing. All of the following registers are located in PCI Memory BAR0 space. A second MCR register has been

added in the BCM5802 to handle the key setup operations. The BCM5802 is completely compatible with the BCM5801 for

crypto/authentication operations. The BCM5801 software driver also works on the BCM5802 without modification

The following table shows the DMA control and status registers.

Table 28:

PCI Memory BAR0 Space DMA Registers

ADDR

Bits

0x00

Master Command Record 1@

0x04

DMA Control

0x08

DMA Status

0x0C

DMA Error Address

0x10

Master Command Record 2@

Table 29:

DMA Control and Status Registers

Bits

Access

Reset

Purpose

DMA Master Command Record 1@: 0x00

31:0

Writing the address of a valid Master Command Record to this register causes crypto/

authentication processing of the packets within that record to begin. This register must

only be written when the MCR_FULL bit of the DMA Status register is 0. This register is

double buffered, such that the MCR_FULL bit goes to zero very quickly after an initial

write. This allows the CPU to write a second MCR address value to this register,

effectively queuing up to MCR structures for back to back processing with zero latency.

Reset state is Unknown. Do not write if PCI master mode is disabled.

DMA Control: 0x04

RESET. Software reset. Normally, it is unset. If software detects hanging or other

undesirable states of BCM5802, it sets this bit to reset. After writing 1 to this bit, you

must wait 30 PCI clocks before the chip can be accessed again.

MCR2INT_EN. Enable interrupt per MCR for MCR2. An interrupt is generated every

time an entire MCR completes processing. This is the preferred operational mode.

Resets to 0.

MCR1INT_EN. Enable interrupt per MCR for MCR1. An interrupt is generated every

time an entire MCR completes processing. This is the preferred operational mode.

Resets to 0.

RSVD

Reserved.

RSVD

Reserved. Do not change its reset value.

RSVD

Reserved. Do not change its reset value.

DMAERR_EN. Enable interrupt upon DMA master access error.

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