Production Specification

07/03/02

B roa dcom Co rpo rat ion

Document

5802-DS03-405-R

1

PCI configuration registers implement control and status information that is specific to the PCI bus, as well as registers

required by the PCI specification revision 2.2.

2

DMA control and status registers correspond to master command, data and packet context fetch and write back

operations.

Unused bits read as an unknown value which could be zero or one, and should be masked off prior to further processing.

Unused bits should be written as zeroes. The following mnemonics are used to describe the types of access allowed for

each register bit:

•

RW: bit is read/write

•

WO: bit is write only

•

RO: read only bit (i.e. status flag)

•

RSVD: reserved bit, ignore upon read, write 0s upon write

A value of X upon reset means that the state of the register is undefined and should not be relied upon after a reset occurs.

Memory BAR0 for all slave control and status registers. The registers use a total memory space of 64 KB in one memory

BAR region. This region is non-pre-fetchable, and must be relocated only in 32-bit space.

Configuration registers not shown in the table below are reserved.

Table 26:

PCI 2.2-Compliant Configuration Space Registers

ADDR

31

Bits

16

15

Bits

00

0x00

Device ID

Vendor ID

0x04

Status

Command

0x08

Class code

Rev ID

0x0C

BIST

Header Type

Master Latency Timer

Cache line Size

0x10

Memory BAR0

0x2C

Subsystem ID

Subsystem Vendor ID

0x3C

MAX_LAT

MIN_GNT

Interrupt Pin

Interrupt Line

0x40

Reserved

Retry Timeout

TRDY Timeout