5802-DS02-R datasheet(10/50 Pages) BOARDCOM

10 / 50 page

■ BCM5802

Production Specification

07/03/02

B roa dcom Co rpo rat ion

Page 2

Key Features and Statistics

Document

5802-DS03-405-R

IETF IPSEC COMPLIANT ACCELERATION

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3DES CBC encryption and decryption in accordance with FIPS 46-3 and FIPS 81.

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HMAC-MD5-96 and HMAC-SHA1-96 authentication in accordance with RFC2403, RFC2404 and FIPS 180-1.

Automatic generation of MD5/SHA1 padding.

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Single-pass encryption and authentication via pipelined application of algorithms over payload in accordance with

RFC2402 and RFC2406.

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Automatic sequencing of encryption and authentication: Encrypt first for outbound packets, authenticate first for

inbound packets in accordance with RFC2401.

IETF IKE

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768-bit and 1024-bit Diffie-Hellman key generations for IKE handshake according to RFC2409

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512-bit, 768-bit and 1024-bit RSA signing and verification for IKE handshake

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1024-bit DSA signing and verification for IKE handshake according to FIPS 186-2

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True random number generation for IKE keys using on-chip random number generator

SECURE SOCKET LAYER (SSL) V 3.0, TRANSPORT LAYER SECURITY (TLS)

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512-bit, 768-bit, and 1024-bit RSA public key and private key processing

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512-bit, 768-bit, and 1024-bit Diffe-Hellman session key generation

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DES and Triple-DES bulk encryption capability

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1024-bit DSA signing and verification

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HMAC-MD5/SHA1 bulk authentication according to RFC2104

STREAMLINED, FLEXIBLE SOFTWARE COMMAND AND PACKET INTERFACE

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Flexible command interface allows exchange of multiple packets or public key setups with one PCI write

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Zero latency command buffer switching via double-buffered master command register

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Support for big and little endian environments

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Host CPU intervention not required between packets or between key setups

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Intelligent, autonomous DMA descriptor based interface to minimize software load

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Scatter/Gather support to eliminate packet data or key setup data copying

–handles fragmented data directly

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Support for any number of IPsec security association contexts, limited only by system memory

ADDITIONAL PERFORMANCE ENHANCING FEATURES

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Latency-tolerant design optimized for shared PCI bus environments. The BCM5802 leverages PCI burst mode access

capability, up to a maximal burst size of 64 bytes.

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Aggressive pre-fetch of command and packet data.

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Full performance is maintained independent of any reasonable PCI latency.

ADVANCED TESTABILITY FEATURES

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100% testability of on-chip RAM cells via BIST circuitry

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JTAG boundary scan for board-level testing

5802-DS02-R 数据表(PDF) 10 Page - Broadcom Corporation.

5802-DS02-R 数据表(HTML) 10 Page - Broadcom Corporation.

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