5802-DS02-R datasheet(46/50 Pages) BOARDCOM

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■ BCM5802

Production Specification

07/03/02

B roa dcom Co rpo rat ion

Page 38 BCM5802 Registers

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5802-DS03-405-R

24:23

RNG_MODE

• 00: 1 bit random number per one slow clock cycle.

• 01: 1 bit random number per four slow clock cycles

• 10: 1 bit random number per eight slow clock cycles

• 11: 1 bit random number per sixteen slow clock cycles

15:0

RSVD

Reserved.

DMA Status: 0x08

Master access in progress. Resets to 0.

MCR1_FULL flag. Master Command Address register is full. When this flag is 1, the

CPU must not write to the MCR1@register. When this flag is 0, the PCU may write a

value to the MCR1@register to request processing of a master command structure.

Resets to 0.

MCR1_INTR. Completion interrupt status of per-MCR interrupt for MCR1. Cleared by

writing a 1 to this bit position.

Note: This bit accurately reflects processing status, even if the corresponding

interrupt bit is disabled (in which case a PCI interrupt is not generated).

This bit is sticky until cleared explicitly. Resets to 0.

DMAERR_INTR. Interrupt status for MCR DMA master access error. Sticky until

software reset (DMA control bit 31 is set to 1) or hardware reset. This bit accurately

reflects status even if the corresponding interrupt enable bit is off (in which case a PCI

interrupt is not generated). Resets to 0.

MCR2_FULL flag. Master Command Address register is full. When this flag is 1, the

CPU must not write to the MCR2@ register. When this flag is 0, the CPU may write a

value to the MCR2@ register to request processing of a master command structure.

Resets to 0.

MCR2_INTR. Completion interrupt status of per-MCR interrupt for MCR2. Cleared by

writing a 1 to this bit position.

Note: This bit accurately reflects processing status (in which case a PCI interrupt is

not generated).

This bit is sticky until cleared explicitly. Resets to 0.

DMA Error Address: 0x0C

31:2

Address of master access that resulted in a PCI fault (32b word address). Reset state

unknown.

1 = faulted master access was a read, 0 = was a write. Reset state unknown.

DMA Master Command Record 2@: 0x10

31:0

Writing the address of a valid Master Command Record to this register causes key

setup processing of the data within that record to begin. This register must only be

written when the MCR_FULL bit of the DMA Status register is 0. This register is double

buffered, such that the MCR_FULL bit goes to zero very quickly after an initial write to

this register. This allows the CPU to write a second MCR address value to this register,

effectively queuing up to MCR structures for back-to-back processing with zero latency.

Reset state is unknown. Do not write if PCI master mode is disabled.

Table 29:

DMA Control and Status Registers (Cont.)

Bits

Access

Reset

Purpose

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