AD6624ASSLASHPCB datasheet(30/40 Pages) AD

30 / 40 page

REV. 0

AD6624A

–30–

for I and 12 more bits for Q). If set to ‘01,’ the serial words are

16 bits wide, and if set to ‘1x’ (x is don’t care), the word length

is 24 bits.

SDFS Mode

Bits 8–7 of register 0xA9 determine how the SFDS behaves in

Serial Bus Master mode. In Serial Slave mode, the frame sync

must be formatted by programming Bits 8–7 to ‘00.’

The first mode is set by programming Bits 8–7 to ‘00’. In this

mode, the SDFS is valid for one complete clock cycle prior to

the data shift. On the next clock cycle, the AD6624A begins

shifting out the digitally processed data stream. Depending on

the bit precision of the serial configuration, either 12, 16, or 24 bits

of I data are shifted out, followed by 12, 16, or 24 bits of Q data.

The second mode is set by programming Bits 8–7 to ‘01.’ In

this mode, the SDFS is high for the entire time that valid bits

are being shifted. The SDFS bit goes high concurrent with the first

bit shifted out of the AD6624A and goes low after the last bit

has been shifted.

The third mode is set by programming Bits 8–7 to ‘1x’ (x is don’t

care). In this mode, the SDFS bit goes high as in the first mode,

one clock cycle prior to the actual data. However, a second

SDFS is inserted one clock cycle prior to the shift of the first Q

bit. In this manner, each word out of the AD6624A is accompa-

nied by an SDFS.

Mapping RCF Data to the BIST Registers

If Bit 9 of 0xA9 is set, RCF data is routed to the BIST registers.

This allows the filter results to be read from the microprocessor

port. This can be useful when the data must be accessed via a

parallel port and the decimation rate is sufficiently high that

throughput does not become an issue.

0x00–0x7F: Coefficient Memory (CMEM)

This is the Coefficient Memory (CMEM) used by the RCF. It

is memory mapped as 128 words by 20 bits. A second 128 words

of RAM may be accessed via this same location by writing Bit 8

of the RCF control register high at channel address 0xA4. The

filter calculated will always use the same coefficients for I and

Q. By using memory from both of these 128 blocks, a filter up

to 160 taps can be calculated. Multiple filters can be loaded and

selected with a single internal access to the Coefficient Offset

0x80: Channel Sleep Register

This register contains the SLEEP bit for the channel. When this

bit is high, the channel is placed in a low power state. When this

bit is low, the channel processes data. Note that in serial slave

mode, the

RESET pin needs to be held low for several SCLK

cycles to ensure that it will program this bit high. This bit can

also be set by accessing the SLEEP register at external address

3. When the external SLEEP register is accessed, all four channels

are accessed simultaneously and the SLEEP bits of the channels

are set appropriately.

0x81: Soft_SYNC Register

This register is used to initiate SYNC events through the micro-

port. If the Hop bit is written high, the Hop Hold-Off Counter

at address 0x84 is loaded and begins to count down. When this

value reaches one, the NCO Frequency register used by the NCO

accumulator, is loaded with the data from channel addresses 0x85

and 0x86. When the Start bit is set high, the Start Hold-Off

Counter is loaded with the value at address 0x83 and begins to

count down. When this value hits one, the Sleep bit in address

0x80 is dropped low and the channel is started.

0x82: Pin_SYNC Register

This register is used to control the functionality of the SYNC

pins. Any of the four SYNC pins can be chosen and monitored

by the channel. The channel can be configured to initiate either

a Start or Hop SYNC event by setting the Hop or Start bit high.

These bits function as enables so that when a SYNC pulse occurs

either the Start or Hop Hold-Off Counters are activated in the

same manner as with a Soft_SYNC.

0x83: Start Hold-Off Counter

The Start Hold-Off Counter is loaded with the value written

to this address when a Start_Sync is initiated. It can be initiated

by either a Soft_SYNC or Pin_SYNC. The counter begins

decrementing and when it reaches a value of one, the channel

is brought out of SLEEP and begins processing data. If the

channel is already running, the phase of the filters is adjusted

such that multiple AD6624s can be synchronized. A periodic

pulse on the SYNC pin can be used in this way to adjust the

timing of the filters with the resolution of the ADC sample

clock. If this register is written to a one, the Start will occur

immediately when the SYNC comes into the channel. If it is

written to a zero, no SYNC will occur.

0x84: NCO Frequency Hold-Off Counter

The NCO Frequency Hold-Off Counter is loaded with the value

written to this address when either a Soft_SYNC or Pin_SYNC

comes into the channel. The counter begins counting down so

that when it reaches one, the NCO Frequency word is updated

with the values of addresses 0x85 and 0x86. This is known as a

Hop or Hop_SYNC. If this register is written to a one, the

NCO Frequency will be updated immediately when the SYNC

comes into the channel. If it is written to a zero, no HOP will

occur. NCO HOPs can be either phase continuous or nonphase

continuous, depending upon the state of Bit 3 of the NCO

control register at channel address 0x88. When this bit is low,

the Phase Accumulator of the NCO is not cleared, but starts to

add the new NCO Frequency word to the accumulator as soon

as the SYNC occurs. If this bit is high, the Phase Accumulator of

the NCO is cleared to zero and the new word is then accumulated.

0x85: NCO Frequency Register 0

This register represents the 16 LSBs of the NCO Frequency word.

These bits are shadowed and are not updated to the register

used for the processing until the channel is either brought out of

SLEEP or a Soft_SYNC or Pin_SYNC has been issued. In the

latter two cases, the register is updated when the Frequency

Hold-Off Counter hits a value of one. If the Frequency Hold-Off

Counter is set to one, the register will be updated as soon as the

shadow is written.

0x86: NCO Frequency Register 1

This register represents the 16 MSBs of the NCO Frequency word.

These bits are shadowed and are not updated to the register used

for the processing until the channel is either brought out of SLEEP

or a Soft_SYNC or Pin_SYNC has been issued. In the latter

two cases, the register is updated only when the Frequency

Hold-Off Counter hits a value of one. If the Frequency Hold-

Off Counter is set to one, the register will be updated as soon as

the shadow is written.

AD6624AS/PCB 数据表(PDF) 30 Page - Analog Devices

AD6624AS/PCB 数据表(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载