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AD6624AS/PCB 数据表(PDF) 4 Page - Analog Devices |
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AD6624AS/PCB 数据表(HTML) 4 Page - Analog Devices |
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4 / 40 page  REV. 0 –4– AD6624A GENERAL TIMING CHARACTERISTICS 1, 2 Test AD6624AS Parameter (Conditions) Temp Level Min Typ Max Unit CLK Timing Requirements: tCLK CLK Period Full I 10 ns tCLKL CLK Width Low Full IV 4.5 0.5 × tCLK ns tCLKH CLK Width High Full IV 4.5 0.5 × t CLK ns RESET Timing Requirement: tRESL RESET Width Low Full I 30.0 ns Input Wideband Data Timing Requirements: tSI Input to ↑CLK Setup Time Full IV 0.8 ns tHI Input to ↑CLK Hold Time Full IV 2.0 ns Level Indicator Output Switching Characteristic: tDLI ↑CLK to LI (A–A, B; B–A, B) Output Delay Time Full IV 3.8 12.6 ns SYNC Timing Requirements: tSS SYNC (A, B, C, D) to ↑CLK Setup Time Full IV 1.0 ns tHS SYNC (A, B, C, D) to ↑CLK Hold Time Full IV 2.0 ns Serial Port Timing Requirements (SBM = 1): Switching Characteristics: 3 tDSCLK1 ↑CLK to ↑SCLK Delay (Divide by 1) Full IV 3.9 13.4 ns tDSCLKH ↑CLK to ↑SCLK Delay (For Any Other Divisor) Full IV 4.4 14.0 ns tDSCLKL ↑CLK to ↓SCLK Delay (Divide by 2 or Even #) Full IV 3.25 6.7 ns tDSCLKLL ↓CLK to ↓SCLK Delay (Divide by 3 or Odd #) Full IV 3.8 6.9 ns tDSDFS ↑SCLK to SDFS Delay Full IV 0.2 5.3 ns tDSDFE ↑SCLK to SDFE Delay Full IV –0.4 +4.7 ns tDSDO ↑SCLK to SDO Delay Full IV –1.0 +4.0 ns tDSDR ↑SCLK to DR Delay Full IV –0.3 +4.6 ns tDDR ↑CLK to DR Delay Full IV 5.4 17.6 ns Input Characteristics: tSSI SDI to ↓SCLK Setup Time Full IV 2.4 ns tHSI SDI to ↓SCLK Hold Time Full IV 3.0 ns Serial Port Timing Requirements (SBM = 0): Switching Characteristics:3 tSCLK SCLK Period Full IV 16 ns tSCLKL SCLK Low Time (When SDIV = 1, Divide by 1) Full IV 5.0 ns tSCLKH SCLK High Time (When SDIV = 1, Divide by 1) Full IV 5.0 ns tDSDFE ↑SCLK to SDFE Delay Full IV 3.8 15.4 ns tDSDO ↑SCLK to SDO Delay Full IV 3.7 15.2 ns tDSDR ↑SCLK to DR Delay Full IV 3.9 15.9 ns Input Characteristics: tSSF SDFS to ↑SCLK Setup Time Full IV 1.9 ns tHSF SDFS to ↑SCLK Hold Time Full IV 0.7 ns tSSI SDI to ↓SCLK Setup Time Full IV 2.4 ns tHSI SDI to ↓SCLK Hold Time Full IV 2.0 ns NOTES 1All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V. 2C LOAD = 40 pF on all outputs unless otherwise specified. 3The timing parameters for SCLK, SDFS, SDFE, SDO, SDI, and DR apply to all four channels (0, 1, 2, and 3). The slave serial port’s (SCLK) operating frequency is limited to 62.5 MHz. Specifications subject to change without notice. |
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