AD6624ASSLASHPCB datasheet(14/40 Pages) AD

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REV. 0

AD6624A

–14–

EXAMPLE FILTER RESPONSE

The filter in Figure 19 is based on a 65 MSPS input data rate

and an output rate of 541.6666 kSPS (two samples per symbol

for EDGE). Total decimation rate is 120 distributed between

the rCIC2, CIC5 and RCF.

kHz

–1000

1000

–800 –600 –400 –200

200

400

600

800

–50

–20

–40

–10

–30

–60

–80

–100

–70

–90

–110

–120

–140

–130

–150

Figure 19. Filter Response

The filter in Figure 20 is designed to meet the IS-136 specifica-

tions. For this configuration, the clock is set to 61.44 MSPS

with a total decimation rate of 320 providing an output data

rate of 192 kSPS or four samples per symbol.

kHz

–500

–400

–200

200

400

500

–50

–20

–40

–10

–30

–60

–80

–100

–70

–90

–110

–120

–140

–130

–150

Figure 20. Filter Response

INPUT DATA PORTS

The AD6624A features dual, high-speed ADC input ports, Input

Port A and Input Port B. The dual input ports allow for the

most flexibility with a single tuner chip. These can be diversity

inputs or truly independent inputs such as separate antenna

segments. Either ADC port can be routed to one of four tuner

channels. For added flexibility, each input port can be used to

support multiplexed inputs such as found on the AD6600 or

other ADCs with mixed outputs. This added flexibility can

allow for up to four different analog sources to be processed

simultaneously by the four internal channels.

In addition, the front end of the AD6624A contains circuitry that

enables high-speed signal level detection and control. This is

accomplished with a unique high-speed level detection circuit

that offers minimal latency and maximum flexibility to control

up to four analog signal paths. The overall signal path latency

from input to output on the AD6624A can be expressed in high-

speed clock cycles. The equation below can be used to calculate

the latency.

SDIV

LATENCY

rC C

CIC

TAPS

()++

()+

MrC1C2 and MCIC5 are decimation values for the rC1C2 and

CIC5 filters respectively, NTAPS is the number RCF taps chosen,

and SDIV is the chosen SCLK divisor factor.

Input Data Format

Each input port consists of a 14-bit mantissa and 3-bit exponent. If

interfacing to a standard ADC is required, the exponent bits can

be grounded. If connected to a floating point ADC such as the

AD6600, the exponent bits from that product can be connected

to the input exponent bits of the AD6624A. The mantissa data

format is two’s-complement and the exponent is unsigned binary.

Input Timing

The data from each high-speed input port is latched on the

rising edge of CLK. This clock signal is used to sample the

input port and clock the synchronous signal processing stages

that follow in the selected channels.

The clock signals can operate up to 80 MHz and have a 50% duty

cycle. In applications using high-speed ADCs, the ADC sample

clock or data valid strobe is typically used to clock the AD6624A.

CLK

IN[13:0]

EXP[2:0]

DATA

tSI

tHI

Figure 21. Input Data Timing Requirements

CLK

tCLK

tCLKH

tCLKL

Figure 22. CLK Timing Requirements

Input Enable Control

There is an IENA and an IENB pin for the Input Port A and

Input Port B respectively. There are four modes of operation

used for each IEN pin. Using these modes, it is possible to

emulate operation of the other RSPs such as the AD6620, which

offer dual channel modes normally associated with diversity

operations. These modes are: IEN transition to low, IEN transi-

tion to high, IEN high, and blank on IEN low.

In the IEN high mode, the inputs and normal operations occur

when the Input Enable is high. In the IEN transition to low

mode, normal operations occur on the first rising edge of the

clock after the IEN transitions to low. Likewise, in the IEN

transition to high mode, operations occur on the rising edge of

the clock after the IEN transitions to high. See the Numerically

Controlled Oscillator section for more details on configuring the

Input Enable Modes. In blank on IEN low mode, the input data

is interpreted as zero when IEN is low.

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