AD6624ASSLASHPCB datasheet(20/40 Pages) AD

20 / 40 page

REV. 0

AD6624A

–20–

Bit 11 of this register is used to invert the external exponent

before internal calculation. This bit should be set HIGH for

gain-ranging ADCs that use an increasing exponent to represent

an increasing signal level. This bit should be set LOW for gain-

ranging ADCs that use a decreasing exponent for representing

an increasing signal level.

In applications that do not require the features of the rCIC2,

it may be bypassed by setting the L/M ratio to 1/1. This effectively

bypasses all circuitry of the rCIC2 except the scaling, which

is still effectual.

FIFTH ORDER CASCADED INTEGRATOR COMB FILTER

The third signal processing stage, CIC5, implements a sharper

fixed-coefficient, decimating filter than CIC2. The input rate to

this filter is fSAMP2. The maximum input rate is given by Equa-

tion 9. NCH equals two for Diversity Channel Real input mode;

otherwise NCH equals one. In order to satisfy this equation, MCIC2

can be increased, NCH can be reduced, or fCLK can be increased

(reference fractional rate input timing described in the Input

Timing section).

SAMP

CLK

≤

(9)

The decimation ratio, MCIC5, may be programmed from 2 to 32

(all integer values). The frequency response of the filter is given

by Equation 10. The gain and passband droop of CIC5 should

be calculated by these equations. Both parameters may be com-

pensated for in the RCF stage.

CIC

()

–

=×









(10)

CIC

SAMP

CIC

()

sin

=×





























The scale factor, SCIC5 is a programmable unsigned integer

between 0 and 20. It serves to control the attenuation of the

data into the CIC5 stage in 6 dB increments. For the best

dynamic range, SCIC5 should be set to the smallest value possible

(lowest attenuation) without creating an overflow condition.

This can be safely accomplished using Equation 11, where

OLrCIC2 is the largest fraction of full scale possible at the input

to this filter stage. This value is output from the rCIC2 stage,

then pipelined into the CIC5.

ceil

CIC

rCIC

CIC

rCIC

CIC

=×

()

= () ×

log (

) –

(11)

The output rate of this stage is given by Equation 12.

SAMP

CIC

≤

(12)

CIC5 Rejection

Table IV illustrates the amount of bandwidth in percentage of

the clock rate that can be protected with various decimation

rates and alias rejection specifications. The maximum input rate

into the CIC5 is 80 MHz when the rC1C2 decimates by one.

As in Table III, these are the 1/2 bandwidth characteristics of

the CIC5. Note that the CIC5 stage can protect a much wider

band than the CIC2 for any given rejection.

Table IV. SSB CIC5 Alias Rejection Table (fSAMP2 = 1)

MCIC5

–50 dB –60 dB

–70 dB

–80 dB –90 dB

–100 dB

10.227

8.078

6.393

5.066

4.008

3.183

7.924

6.367

5.11

4.107

3.297

2.642

6.213

5.022

4.057

3.271

2.636

2.121

5.068

4.107

3.326

2.687

2.17

1.748

4.267

3.463

2.808

2.27

1.836

1.48

3.68

2.989

2.425

1.962

1.588

1.281

3.233

2.627

2.133

1.726

1.397

1.128

2.881

2.342

1.902

1.54

1.247

1.007

2.598

2.113

1.716

1.39

1.125

0.909

2.365

1.924

1.563

1.266

1.025

0.828

2.17

1.765

1.435

1.162

0.941

0.76

2.005

1.631

1.326

1.074

0.87

0.703

1.863

1.516

1.232

0.998

0.809

0.653

1.74

1.416

1.151

0.932

0.755

0.61

1.632

1.328

1.079

0.874

0.708

0.572

1.536

1.25

1.016

0.823

0.667

0.539

1.451

1.181

0.96

0.778

0.63

0.509

1.375

1.119

0.91

0.737

0.597

0.483

1.307

1.064

0.865

0.701

0.568

0.459

1.245

1.013

0.824

0.667

0.541

0.437

1.188

0.967

0.786

0.637

0.516

0.417

1.137

0.925

0.752

0.61

0.494

0.399

1.09

0.887

0.721

0.584

0.474

0.383

1.046

0.852

0.692

0.561

0.455

0.367

1.006

0.819

0.666

0.54

0.437

0.353

0.969

0.789

0.641

0.52

0.421

0.34

0.934

0.761

0.618

0.501

0.406

0.328

0.902

0.734

0.597

0.484

0.392

0.317

0.872

0.71

0.577

0.468

0.379

0.306

0.844

0.687

0.559

0.453

0.367

0.297

0.818

0.666

0.541

0.439

0.355

0.287

This table helps to calculate an upper bound on decimation,

MCIC5, given the desired filter characteristics.

RAM COEFFICIENT FILTER

The final signal processing stage is a sum-of-products decimat-

ing filter with programmable coefficients (see Figure 27). The

data memories I-RAM and Q-RAM store the 160 most recent

complex samples from the previous filter stage with 20-bit

resolution. The coefficient memory, CMEM, stores up to 256

coefficients with 20-bit resolution. On every CLK cycle, one tap

for I and one tap for Q are calculated using the same coefficients.

The RCF output consists of 24-bit data bits.

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