AD6624ASSLASHPCB datasheet(8/40 Pages) AD

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REV. 0

AD6624A

–8–

TIMING DIAGRAMS—INM MICROPORT MODE

CLK

RD(DS)

WR(RW)

A[2:0]

D[7:0]

RDY

(

DTACK)

tSC

tHC

tHWR

tSAM

tHAM

tDRDY

VALID DATA

VALID ADDRESS

tHAM

tACC

NOTES

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

MEASURED FROM FE OF

WR TO THE RE OF RDY.

2. tACC REQUIRES A MAXIMUM 9 CLK PERIODS.

Figure 14. INM Microport Write Timing Requirements

CLK

RD (DS)

WR(RW)

A[2:0]

D[7:0]

RDY

(

DTACK)

tSC

tSAM

tZD

tDRDY

VALID DATA

VALID ADDRESS

tACC

tHC

tZD

tHAM

NOTES

tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS

TIME IS MEASURED FROM FE OF

WR TO THE RE OF RDY.

tACC REQUIRES A MAXIMUM OF 13 CLK PERIODS AND APPLIES TO

A[2:0] = 7, 6, 5, 3, 2, 1

tDD

Figure 15. INM Microport Read Timing Requirements

TIMING DIAGRAMS—MNM MICROPORT MODE

CLK

DS(RD)

A[2:0]

D[7:0]

DTACK

(RDY)

tSC

tHC

tHRW

tSAM

tHAM

VALID DATA

VALID ADDRESS

tHAM

tACC

NOTES

tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

MEASURED FROM FE OF

DS TO THE FE OF DTACK.

tACC REQUIRES A MAXIMUM 9 CLK PERIODS.

RW(

WR)

tDDTACK

tHDS

Figure 16. MNM Microport Write Timing Requirements

CLK

RD(DS)

WR(RW)

A[2:0]

D[7:0]

DTACK

(RDY)

tSC

tSAM

tZD

VALID DATA

VALID ADDRESS

tACC

tHC

tZD

tHAM

tDD

tDDTACK

tHDS

NOTES

tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

MEASURED FROM FE OF

DS TO THE FE OF DTACK.

tACC REQUIRES A MAXIMUM 13 CLK PERIODS.

Figure 17. MNM Microport Read Timing Requirements

AD6624AS/PCB 数据表(PDF) 8 Page - Analog Devices

AD6624AS/PCB 数据表(HTML) 8 Page - Analog Devices

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AD6624AS/PCB 数据表(PDF) 8 Page - Analog Devices

AD6624AS/PCB 数据表(HTML) 8 Page - Analog Devices

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