AD6624ASSLASHPCB datasheet(34/40 Pages) AD

34 / 40 page

REV. 0

AD6624A

–34–

Access Control Register (ACR)

The Access Control Register serves to define the channel or

channels that receive an access from the microport or Serial Port 0.

Bit 7 of this register is the autoincrement bit. If this bit is a 1,

the CAR register described below will increment its value after

every access to the channel. This allows blocks of address space

such as Coefficient Memory to be initialized more efficiently.

Bit 6 of the register is the broadcast bit and determines how Bits

5–2 are interpreted. If broadcast is 0, Bits 5–2, which are referred

to as instruction bits (Instruction [3:0]), are compared with the

CHIP_ID [3:0] pins. The instruction that matches the CHIP_ID

[3:0] pins will determine the access. This allows up to 16 chips

to be connected to the same port and memory mapped without

external logic. This also allows the same serial port of a host

processor to configure up to 16 chips. If the broadcast bit is

high, the Instruction [3:0] word allows multiple AD6624A

channels and/or chips to be configured simultaneously, indepen-

dent of the CHIP_ID[3:0] pins. Ten possible instructions are

defined in Table XII. This is useful for smart antenna systems

where multiple channels listening to a single antenna or carrier

can be simultaneously configured. The x(s) in the table represent

“don’t cares” in the digital decoding.

Table XII. Microport Instructions

Instruction

Comment

0000

All chips and all channels will get the access.

0001

Channel 0, 1, 2 of all chips will get the access.

0010

Channel 1, 2, 3 of all chips will get the access.

0100

All chips will get the access.

1000

All chips with Chip_ID[3:0] = xxx0 will get

the access.

1001

All chips with Chip_ID[3:0] = xxx1 will get

the access.

1100

All chips with Chip_ID[3:0] = xx00 will get

the access.

1101

All chips with Chip_ID[3:0] = xx01 will get

the access.

1110

All chips with Chip_ID[3:0] = xx10 will get

the access.

1111

All chips with Chip_ID[3:0] = xx11 will get

the access.

*A[9:8] bits control which channel is decoded for the access.

External Memory Map

When broadcast is enabled (Bit 6 set high), readback is not valid

because of the potential for internal bus contention. Therefore,

if readback is subsequently desired, the broadcast bit should

be set low.

Bits 1–0 of this register are address bits that decode which of the

four channels are being accessed. If the Instruction bits decode

an access to multiple channels, these bits are ignored. If the

Instruction decodes an access to a subset of chips, the A[9:8] bits

will otherwise determine the channel being accessed.

Channel Address Register (CAR)

This register represents the 8-bit internal address of each channel.

If the autoincrement bit of the ACR is 1, this value will be incre-

mented after every access to the DR0 register, which will in

turn access the location pointed to by this address. The Channel

Address register cannot be read back while the broadcast bit

is set high.

SOFT_SYNC Control Register

External Address [5] is the SOFT_SYNC control register and is

write only.

Bits 0–3 of this register are the SOFT_SYNC control bits. These

pins may be written to by the controller to initiate the synchro-

nization of a selected channel. Although there are four inputs,

these do not necessarily go to the channel of the same number.

This is fully configurable at the channel level as to which bit to

look at. All four channels may be configured to synchronize from a

single position, or they may be paired or all independent.

Bit 4 determines if the synchronization is to apply to a chip

start. If this bit is set, a chip start will be initiated.

Bit 5 determines if the synchronization is to apply to a chip hop.

If this bit is set, the NCO frequency will be updated when the

SOFT_SYNC occurs.

Bit 6 configures how the internal data bus is configured. If this

bit is set low, the internal ADC data buses are configured nor-

mally. If this bit is set, the internal test signals are selected. The

internal test signals are configured in Bit 7 of this register.

Bit 7 if set clear, a negative full-scale signal is generated and

made available to the internal data bus. If this bit is high, inter-

nal pseudo-random sequence generator is enabled and this data

is available to the internal data bus. The combined functions of

Bits 6 and 7 facilitate verification of a given filter design. Also,

in conjunction with the MISR registers, allow for detailed in-

system chip testing. In conjunction with the JTAG test board,

very high levels of chip verification can be done during system

test, in both the factory and field.

PIN_SYNC Control Register

External Address [4] is the PIN_SYNC control register and is

write only.

Bits 0–3 of this register are the SYNC_EN control bits. These

pins may be written to by the controller to allow pin synchro-

nization of a selected channel. Although there are four inputs,

these do not necessarily go to the channel of the same number.

This is fully configurable at the channel level as to which bit to

look at. All four channels may be configured to synchronize

from a single position, or they may be paired or all independent.

Bit 4 determines if the synchronization is to apply to a chip

start. If this bit is set, a chip start will be initiated when the

PIN_SYNC occurs.

Bit 5 determines if the synchronization is to apply to a chip hop.

If this bit is set, the NCO Frequency will be updated when the

when the PIN_SYNC occurs.

Bit 6 is used to ignore repetitive synchronization signals. In

some applications, this signal may occur periodically. If this bit

is clear, each PIN_SYNC will restart/hop the channel. If this bit

is set, only the first occurrence will cause the chip to take action.

Bit 7 is used with Bits 6 and 7 of external address 5. When this

bit is cleared, the data supplied to the internal data bus simulates a

normal ADC. When this bit is set, the data supplied is in the

form of a time-multiplexed ADC such as the AD6600 (this

allows the equivalent of testing in the 4-channel input mode).

Internally, when set, this bit forces the IEN pin to toggle as if it

were driven by the A/B signal of the AD6600.

SLEEP Control Register

External Address [3] is the sleep register.

AD6624AS/PCB 数据表(PDF) 34 Page - Analog Devices

AD6624AS/PCB 数据表(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载

链接网址

AD6624AS/PCB 数据表(PDF) 34 Page - Analog Devices

AD6624AS/PCB 数据表(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表 下载

链接网址

数据表下载