AD6624ASSLASHPCB datasheet(37/40 Pages) AD

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AD6624A

–37–

JTAG BOUNDARY SCAN

The AD6624A supports a subset of IEEE Standard 1149.1 specifi-

cations. For additional details of the standard, please see “IEEE

Standard Test Access Port and Boundary-Scan Architecture,”

IEEE-1149 publication from IEEE.

The AD6624A has five pins associated with the JTAG interface.

These pins are used to access the on-chip Test Access Port and

are listed in the table below. All input JTAG pins are pull-up,

except for TCLK which has a pull-down.

Table XIV. Boundary Scan Test Pins

Name

Pin Number

Description

TRST

Test Access Port Reset

TCLK

Test Clock

TMS

Test Access Port Mode Select

TDI

Test Data Input

TDO

Test Data Output

The AD6624A supports the op codes as shown below. These

instructions set the mode of the JTAG interface.Address 02 is

the dwell time for input channel A. This sets the

Table XV. Boundary Scan Op Codes

Instruction

Op Code

IDCODE

001

BYPASS

111

SAMPLE/PRELOAD

010

EXTEST

000

HIGHZ

011

CLAMP

100

The Vendor Identification Code can be accessed through the

IDCODE instruction and has the following format.

Table XVI. Vendor ID Code

MSB

Part

Manufacturing

LSB

Version

Number

ID #

Mandatory

0000

0010

000 1110 0101

0111

1000

1100

A BSDL file for this device is available; please contact Analog

Devices, Inc. for more information.

EXTEST (3’b000) Places the IC into an external boundary-test

mode and selects the boundary-scan register to be connected

between TDI and TDO. During this, the boundary-scan regis-

ter is accessed to drive test data off-chip via boundary outputs

and receive test data off-chip from boundary inputs.

IDCODE (3’b001) Allows the IC to remain in its functional

mode and selects device ID register to be connected between

TDI and TDO. Accessing the ID register does not interfere

with the operation of the IC.

SAMPLE/PRELOAD (3’b010) Allows the IC to remain in

normal functional mode and selects the boundary-scan register

to be connected between TDI and TDO. The boundary-scan

the functional data entering and leaving the IC. Also, test

data can be preloaded into the boundary scan register before

an EXTEST instruction.

HIGHZ (3’b011) Sets all outputs to high impedance state.

Selects the 1-bit bypass register to be connected between

TDI and TDO.

CLAMP (3’b100) Sets the outputs of the IC to logic levels

determined by the boundary-scan register and selects the 1-bit

bypass register to be connected between TDI and TDO. Before

this instruction, boundary-scan data can be preloaded with

the SAMPLE/PRELOAD instruction.

BYPASS (3’b111) Allows the IC to remain in normal functional

mode and selects 1-bit bypass register between TDI and TDO.

During this instruction, serial data is transferred from TDI to

TDO without affecting operation of the IC.

INTERNAL WRITE ACCESS

Up to 20 bits of data (as needed) can be written by the process

described below. Any high order bytes that are needed are writ-

ten to the corresponding data registers defined in the external

3-bit address space. The least significant byte is then written to

DR0 at address (000). When a write to DR0 is detected, the

internal microprocessor port state machine then moves the data

in DR2-DR0 to the internal address pointed to by the address in

the LAR and AMR.

Write Pseudocode

void write_micro(ext_address, int data);

main();

{

* This code shows the programming of the NCO phase offset

variable address is the External Address A[2:0] and data is the

value to be placed in the external interface register.

Internal Address = 0x087

// holding registers for NCO phase byte wide access data

int d1, d0;

// NCO frequency word (16-bits wide)

NCO_PHASE = 0xCBEF;

// write ACR

write_micro(7, 0x03);

// write CAR

write_micro(6, 0x03);

// write DR1 with D[15:8]

d1 = (NCO_PHASE & 0xFF00) >> 8;

write_micro(1, d1);

// write DR0 with D[7:0]

// On this write all data is transferred to the internal address

d0 = NCO_FREQ & 0xFF;

write_micro(0, d0);

} // end of main

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