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AD6624AS/PCB 数据表(PDF) 19 Page - Analog Devices |
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AD6624AS/PCB 数据表(HTML) 19 Page - Analog Devices |
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19 / 40 page ![]() REV. 0 AD6624A –19– where input_level is the largest fraction of full-scale possible at the input to the AD6624A (normally 1). The rCIC2 scale factor is always used whether or not the rCIC2 is bypassed. Moreover, there are two scale registers (rCIC2_LOUD[4:0] Bits 4–0 in x92), and (rCIC2_QUIET[4:0] Bits 9–5 in 0x92) that are used in conjunction with the computed SrCIC2 which determines the overall rCIC2 scaling. The SrCIC2 value must be summed with the values in each respective scale register and ExpOff, to determine the scale value that must be placed in the rCIC2 scale register. This number must be less than 32 or the interpolation and decimation rates must be adjusted to validate this equation. The ceil function denotes the next whole integer and the floor function denotes the previous whole integer. For example, the ceil(4.5) is 5 while the floor(4.5) is 4. The gain and passband droop of the rCIC2 should be calculated by the equations above, as well as the filter transfer equations that follow. Excessive passband droop can be compensated for in the RCF stage by peaking the passband by the inverse of the roll-off. scaled input IN ExpInv scaled input IN ExpInv Exp rCIC Exp rCIC _, _, mod( , ) mod( , ) =× = =× = −+ −− + 20 21 28 72 8 (7) where: IN is the value of IN[15:0], Exp is the value of EXP[2:0], and rCIC2 is the value of the 0x92 (rCIC2_QUIET[4:0] and rCIC2_LOUD[4:0]) scale register. rCIC2 Rejection Table III illustrates the amount of bandwidth in percent of the data rate into the rCIC2 stage. The data in this table may be scaled to any other allowable sample rate up to 80 MHz in Single Channel Mode or 40 MHz in Diversity Channel Mode. The table can be used as a tool to decide how to distribute the decimation between rCIC2, CIC5, and the RCF. Table III. SSB rCIC2 Alias Rejection Table (fSAMP = 1) Bandwidth Shown in Percentage of fSAMP MCIC5/ LrCIC2 –50 dB –60 dB –70 dB –80 dB –90 dB –100 dB 2 1.79 1.007 0.566 0.318 0.179 0.101 3 1.508 0.858 0.486 0.274 0.155 0.087 4 1.217 0.696 0.395 0.223 0.126 0.071 5 1.006 0.577 0.328 0.186 0.105 0.059 6 0.853 0.49 0.279 0.158 0.089 0.05 7 0.739 0.425 0.242 0.137 0.077 0.044 8 0.651 0.374 0.213 0.121 0.068 0.038 9 0.581 0.334 0.19 0.108 0.061 0.034 10 0.525 0.302 0.172 0.097 0.055 0.031 11 0.478 0.275 0.157 0.089 0.05 0.028 12 0.439 0.253 0.144 0.082 0.046 0.026 13 0.406 0.234 0.133 0.075 0.043 0.024 14 0.378 0.217 0.124 0.07 0.04 0.022 15 0.353 0.203 0.116 0.066 0.037 0.021 16 0.331 0.19 0.109 0.061 0.035 0.02 Example Calculations Goal: Implement a filter with an Input Sample Rate of 10 MHz requiring 100 dB of alias rejection for a ±7 kHz passband. Solution: First determine the percentage of the sample rate that is represented by the passband. BW kHz MHz FRACTION =× = 100 7 10 007 . (8) Find the –100 dB column in Table III and look down this column for a value greater than or equal to your passband percentage of the clock rate. Then look across to the extreme left column and find the corresponding rate-change factor (MrCIC2/LrCIC2). Refer- ring to the table, notice that for a MrCIC2/LrCIC2 of 4, the frequency having –100 dB of alias rejection is 0.071 percent, which is slightly greater than the 0.07 percent calculated. Therefore, for this example, the maximum bound on rCIC2 rate change is 4. A higher chosen MrCIC2/LrCIC2 means less alias rejection than the 100 dB required. An MrCIC2/LrCIC2 of less than four would still yield the required rejection; however, the power consumption can be minimized by decimating as much as possible in this rCIC2 stage. Decima- tion in rCIC2 lowers the data rate, and thus reduces power consumed in subsequent stages. It should also be noted that there is more than one way to determine the decimation by 4. A decimation of 4 is the same as an L/M ratio of 0.25. Thus any integer combination of L/M that yields 0.25 will work (1/4, 2/8, or 4/16). However, for the best dynamic range, the simplest ratio should be used. For example, 1/4 gives better performance than 4/16. Decimation and Interpolation Registers rCIC2 decimation values are stored in register 0x90. This is a 12-bit register and contains the decimation portion less 1. The interpolation portion is stored in register 0x91. This 9-bit value holds the interpolation less one. rCIC2 Scale Register 0x92 contains the scaling information for this section of the circuit. The primary function is to store the scale value computed in the sections above. Bits 4–0 (rCIC2_LOUD[4:0]) of this register are used to con- tain the scaling factor for the rCIC2 during conditions of strong signals. These five bits represent the rCIC2 scalar calculated above plus any external signal scaling with an attenuator. Bits 9–5 (rCIC2_QUIET[4:0]) of this register are used to con- tain the scaling factor for the rCIC2 during conditions of weak signals. In this register, no external attenuator would be used and is not included. Only the value computed above is stored in these bits. Bit 10 of this register is used to indicate the value of the external exponent. If this bit is set LOW, each external exponent repre- sents 6 dB per step as in the AD6600. If this bit is set to HIGH, each exponent represents a 12 dB step. S ceil M floor M L M L floor M L OL M L input level rCIC rCIC rCIC rCIC rCIC rCIC rCIC rCIC CIC rCIC rCIC SrCIC 22 2 2 2 22 2 2 2 2 2 2 21 2 2 =+ ×× − × + = × × log () _ (6) |
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