AD6624ASSLASHPCB datasheet(22/40 Pages) AD

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REV. 0

AD6624A

–22–

Bit 8 is the RCF bank select bit used to program the register.

When this bit is 0, the lowest block of 128 is selected (Taps 0

through 127). When high, the highest block is selected (Taps

128 through 255). It should be noted that while the chip is

computing filters, Tap 127 is adjacent to 128 and there are no

paging issues.

Bit 9 selects the origin of the input to each RCF. If Bit 9 is

clear, the RCF input comes from the CIC5 normally associated

with the RCF. If, however, the bit is set, the input comes from

CIC5 Channel 1. The only exception is Channel 1, which uses

the output of CIC5 Channel 0 as its alternate. Using this feature,

each RCF can either operate on its own channel data or be

paired with the RCF of Channel 1. The RCF of Channel 1 can

also be paired with Channel 0. This control bit is used with

polyphase distributed filtering.

If Bit 10 is clear, the AD6624A channel operates in normal mode.

However, if Bit 10 is set, the RCF is bypassed to Channel BIST.

See BIST (Built In Self-Test) section below for more details.

USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST)

The AD6624A includes two built-in test features to test the

integrity of each channel. The first is a RAM BIST, which is

intended to test the integrity of the high-speed random access

memory within the AD6624A. The second is Channel BIST,

which is designed to test the integrity of the main signal paths

of the AD6624A. Each BIST function is independent of the

other, meaning that each channel can be tested independently

at the same time.

RAM BIST

The RAM BIST can be used to validate functionality of the

on-chip RAM. This feature provides a simple pass/fail test,

which will give confidence that the channel RAM is operational.

The following steps should be followed to perform this test.

• The channels to be tested should be put into Sleep mode via

the external address register 0x011.

• The RAM BIST Enable bit in the RCF register xA8 should

be set high.

• Wait 1600 clock cycles.

• Register 0xA8 should be read back. If Bit 0 is high, the test is

not yet complete. If Bit 0 is low, the test is complete and Bits

1 and 2 indicate the condition of the internal RAM. If Bit 1

is high, CMEM is bad. If Bit 2 is high, DMEM is bad.

Table VII. BIST Register 0xA8

Coefficient MEM

Data MEM

XX1

Test Incomplete

000

Pass

010

Fail

Pass

100

Pass

Fail

110

Fail

CHANNEL BIST

The Channel BIST is a thorough test of the selected AD6624A

signal path. With this test mode, it is possible to use externally

supplied vectors or an internal pseudo-random generator. An

error signature register in the RCF monitors the output data of

the channel and is used to determine if the proper data exits

the RCF. If errors are detected, each internal block may be

bypassed and another test can be run to debug the fault. The

I and Q paths are tested independently. The following steps

should be followed to perform this test.

• The channels to be tested should be configured as required

for the application setting the decimation rates, scalars, and

RCF coefficients.

• The channels should remain in the Sleep mode.

• The Start Hold-Off counter of the channels to be tested

should be set to 1.

• Memory location 0xA5 and 0xA6 should be set to 0.

• The Channel BIST located at 0xA7 should be enabled by

setting Bits 19–0 to the number of RCF outputs to observe.

• Bit 4 of external address register 5 should be set high to start

the soft sync.

• Set the SYNC bits high for the channels to be tested.

• Bit 6 must be set to 0 to allow the user to provide test vectors.

The internal pseudo-random number generator may also be

used to generate an input sequence by setting Bit 7 high.

• An internal –FS sine can be inserted when Bit 6 is set to 1

and Bit 7 is cleared.

• When the SOFT_SYNC is addressed, the selected channels

will come out of the Sleep mode and processing will occur.

• If the user is providing external vectors, the chip may be

brought out of Sleep mode by one of the other methods,

provided that either of the IEN inputs is inactive until the

channel is ready to accept data.

• After a sufficient amount of time, the Channel BIST Signa-

ture registers 0xA5 and 0xA6 will contain a numeric value

that can be compared to the expected value for a known

good AD6624A with the exact same configuration. If the

values are the same, there is a very low probability that there

is an error in the channel.

CHIP SYNCHRONIZATION

Two types of synchronization can be achieved with the AD6624A.

These are Start and Hop. Each is described in detail below. The

synchronization is accomplished with the use of a shadow register

and a hold-off counter. See Figure 28 for a simplistic schematic

of the NCO shadow register and NCO Freq Hold-Off counter

to understand basic operation. Enabling the clock (AD6624A

CLK) for the hold-off counter can occur with either a Soft_Sync

(via the microport), or a Pin Sync (via any of the four AD6624A

SYNC Pins A, B, C, and D). The functions that include shadow

registers to allow synchronization include:

1. Start

2. Hop (NCO Frequency)

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