AD6624ASSLASHPCB datasheet(18/40 Pages) AD

18 / 40 page

REV. 0

AD6624A

–18–

lowered, input data is replaced with zero values. During this

period, the NCO continues to run such that when the IEN line

is raised again, the NCO value will be at the value it would have

otherwise been in had the IEN line never been lowered. This

mode has the effect of blanking the digital inputs when the IEN

line is lowered. Back end processing (rCIC2, CIC5, and RCF)

continues while the IEN line is high. This mode is useful for

time division multiplexed applications.

Mode 01: Clock On IEN High

In this mode, data is clocked into the chip while the IEN line is

high. During the period of time when the IEN line is high, new

data is strobed on each rising edge of the input clock. When

IEN line is lowered, input data is no longer latched into the

channel. Additionally, NCO advances are halted. However,

back end processing (rCIC2, CIC5, and RCF) continues during

this period. The primary use for this mode is to allow for a clock

that is faster than the input sample data rate to allow more filter

taps to be computed than would otherwise be possible. In Fig-

ure 26, input data is strobed only during the period of time when

IEN is high, despite the fact that the CLK continues to run at a

rate four times faster than the data.

CLK

tHI

tSI

n+1

IN[13:0]

E[2:0]

IEN

Figure 26. Fractional Rate Input Timing (4

× CLK) in

Mode 01

Mode 10: Clock on IEN Transition to High

In this mode, data is clocked into the chip only on the first clock

edge after the rising transition of the IEN line. Although data is

only latched on the first valid clock edge, the back end process-

ing (rCIC2, CIC5, and RCF) continues on each available clock

that may be present, similar to Mode 01. The NCO phase accu-

mulator is incremented only once for each new input data sample

and not once for each input clock.

Mode 11: Clock on IEN Transition to Low

In this mode, data is clocked into the chip only on the first clock

edge after the falling transition of the IEN line. Although data is

only latched on the first valid clock edge, the back end process-

ing (rCIC2, CIC5, and RCF) continues on each available clock

that may be present, similar to Mode 01. The NCO phase accu-

mulator is incremented only once for each new input data sample

and not once for each input clock.

WB Input Select

Bit 6 in this register controls which input port is selected for

signal processing. If this bit is set high, Input Port B (INB,

EXPB, and IENB) is connected to the selected filter channel. If

this bit is cleared, Input Port A (INA, EXPA, and IENA) is

connected to the selected filter channel.

Sync Select

Bits 7 and 8 of this register determine which external sync pin is

associated with the selected channel. The AD6624A has four sync

pins named SYNCA, SYNCB, SYNCC, and SYNCD. Any of

these sync pins can be associated with any of the four receiver

channels within the AD6624A. Additionally, if only one sync

signal is required for the system, all four receiver channels can

reference the same sync pulse. Bit value 00 is Channel A, 01 is

Channel B, 10 is Channel C, and 11 is Channel D.

SECOND ORDER rCIC FILTER

The rCIC2 filter is a second order cascaded resampling integra-

tor comb filter. The resampler is implemented using a unique

technique, which does not require the use of a high-speed clock,

thus simplifying the design and saving power. The resampler

allows for noninteger relationships between the master clock

and the output data rate. This allows easier implementation of

systems that are either multimode or require a master clock that

is not a multiple of the data rate to be used.

Interpolation up to 512, and decimation up to 4096, is allowed

in the rCIC2. The resampling factor for the rCIC2 (L) is a 9-bit

integer. When combined with the decimation factor M, a 12-bit

number, the total rate change can be any fraction in the form of:

rCIC

≤

(3)

The only constraint is that the ratio L/M must be less than or

equal to one. This implies that the rCIC2 decimates by 1 or more.

Resampling is implemented by apparently increasing the input

sample rate by the Factor L, using zero stuffing for the new data

samples. Following the resampler is a second order cascaded

integrator comb filter. Filter characteristics are determined only

by the fractional rate change (L/M).

The filter can process signals at the full rate of the input port

80 MHz. The output rate of this stage is given by Equation 4.

SAMP

rCIC

SAMP

rCIC

(4)

Both LrCIC2 and MrCIC2 are unsigned integers. The interpolation

rate (LrCIC2) may be from 1 to 512 and the decimation (MrCIC2)

may be between 1 and 4096. The stage can be bypassed by

setting the decimation to 1/1.

The frequency response of the rCIC2 filter is given by Equation 5.

rCIC

SAMP

rCIC

()

sin

–

−













































−

(5)

The scale factor, SrCIC2 is a programmable, unsigned 5-bit value

between 0 and 31. This serves as an attenuator that can reduce

the gain of the rCIC2 in 6 dB increments. For the best dynamic

range, SrCIC2 should be set to the smallest value possible (i.e.,

lowest attenuation) without creating an overflow condition.

This can be safely accomplished using the following equation:

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