AD6624ASSLASHPCB datasheet(17/40 Pages) AD

17 / 40 page

REV. 0

AD6624A

–17–

It also allows the AD6624A to be tailored in a system that employs

the AD6600, but does not utilize all of its signal range. For

example, if only the first four RSSI ranges are expected to occur,

the ExpOff could be adjusted to five, which would then make

RSSI = 4 correspond to the 0 dB point of the AD6624A.

D10 (MSB)

AD6600

D0 (LSB)

AD6624A

IN13

IN2

IN1

IN0

IEN

EXP2

EXP1

EXP0

RSSI2

RSSI1

RSSI0

AB_OUT

Figure 25. Typical Interconnection of the AD6600 Gain-

Ranging ADC and the AD6624A

NUMERICALLY CONTROLLED OSCILLATOR

Frequency Translation

This processing stage comprises a digital tuner consisting of two

multipliers and a 32-bit complex NCO. Each channel of the

AD6624A has an independent NCO. The NCO serves as a

quadrature local oscillator capable of producing an NCO frequency

between –CLK/2 and +CLK/2 with a resolution of CLK/2

32 in the

complex mode. The worst-case spurious signal from the NCO is

better than –100 dBc for all output frequencies.

The NCO frequency value in registers 0x85 and 0x86 are inter-

preted as a 32-bit unsigned integer. The NCO frequency is

calculated using the equation below.

NCO FREQ

CLK

CHANNEL

_mod

=×









(2)

NCO_FREQ is the 32-bit integer (Registers 0x85 and 0x86),

fCHANNEL is the desired channel frequency, and

CLK

* is the AD6624A master clock rate (CLK).

NCO Frequency Hold-Off Register

When the NCO Frequency registers are written, data is actually

passed to a shadow register. Data may be moved to the main

registers by one of two methods. The first is to start the chip

using the soft sync feature, which will directly load the NCO

registers. The second allows changes to be pre-written and then

updated through direct software control. To accomplish this,

there is an NCO Frequency Hold-Off Counter. The counter

(0x84) is a 16-bit unsigned integer and is clocked at the master

CLK rate. This hold-off counter is also used in conjunction with

the frequency hopping feature of this chip.

Phase Offset

The phase offset register (0x87) adds an offset to the phase

accumulator of the NCO. This is a 16-bit register and is inter-

preted as a 16-bit unsigned integer. A 0x0000 in this register

corresponds to a 0 radian offset and a 0xFFFF corresponds to

an offset of 2

π (1–1/(216)) radians. This register allows multiple

NCOs to be synchronized to produce sine waves with a known

and steady phase difference.

NCO Control Register

The NCO control register located at 0x88 is used to configure

the features of the NCO. These are controlled on a per-channel

basis. These are described below.

Bypass

The NCO in the front end of the AD6624A can be bypassed.

Bypass mode is enabled by setting Bit 0 of 0x88 high. When

they are bypassed, down conversion is not performed and the

AD6624A channel functions simply as a real filter on complex

data. This is useful for passband sampling application where the

A input is connected to the I signal path within the filter and the

B input is connected to the Q signal path. This may be desired if

the digitized signal has already been converted to passband in

prior analog stages or by other digital preprocessing.

Phase Dither

The AD6624A provides a phase dither option for improving the

spurious performance of the NCO. Phase dither is enabled by

setting Bit 1. When phase dither is enabled by setting this bit

high, spurs due to phase truncation in the NCO are randomized.

The energy from these spurs is spread into the noise floor and

Spurious Free Dynamic Range is increased at the expense of

very slight decreases in the SNR. The choice of whether phase

dither is used in a system will ultimately be decided by the system

goals. If lower spurs are desired at the expense of a slightly raised

noise floor, it should be employed. If a low noise floor is desired

and the higher spurs can be tolerated or filtered by subsequent

stages, phase dither is not needed.

Amplitude Dither

Amplitude dither can also be used to improve spurious perfor-

mance of the NCO. Amplitude dither is enabled by setting Bit 2.

Amplitude dither improves performance by randomizing the

amplitude quantization errors within the angular to Cartesian

conversion of the NCO. This option may reduce spurs at the

expense of a slightly raised noise floor. Amplitude dither and

phase dither can be used together, separately, or not at all.

Clear Phase Accumulator on HOP

When Bit 3 is set, the NCO phase accumulator is cleared prior

to a frequency hop. This ensures a consistent phase of the NCO

on each hop. The NCO phase offset is unaffected by this setting

and is still in effect. If phase-continuous hopping is desired, this

bit should be cleared and the last phase in the NCO phase regis-

ter will be the initiating point for the new frequency.

Input Enable Control

There are four different modes of operation for the input enable.

Each of the high-speed input ports includes an IEN line. Any of

the four filter channels can be programmed to take data from

either of the two A or B Input Ports (see WB Input Select section).

Along with data is the IEN(A, B) signal. Each filter channel can

be configured to process the IEN signal in one of four modes.

Three of the modes are associated with when data is processed

based on a time division multiplexed data stream. The fourth

mode is used in applications that employ time division duplex

such as radar, sonar, ultrasound, and communications that

involve TDD.

Mode 00: Blank On IEN Low

In this mode, data is blanked while the IEN line is low. During the

period of time when the IEN line is high, new data is strobed

on each rising edge of the input clock. When the IEN line is

*See NCO Mode Control section.

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