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LPC47M14X 数据表(PDF) 98 Page - SMSC Corporation |
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LPC47M14X 数据表(HTML) 98 Page - SMSC Corporation |
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98 / 205 page ![]() SMSC DS – LPC47M14X Page 98 Rev. 03/19/2001 6.11 SERIAL IRQ The LPC47M14x supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. Timing Diagrams For SER_IRQ Cycle A) Start Frame timing with source sampled a low pulse on IRQ1 RT S RT S SER_IRQ PCI_CLK Host Controller IRQ1 IRQ1 Drive Source RT None IRQ0 FRAME IRQ1 FRAME S RT IRQ2 FRAME None START START FRAME H SL or H 1 Note: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design. B) Stop Frame Timing with Host using 17 SER_IRQ sampling period S RT S SER_IRQ PCI_CLK Host Controller IRQ15 Driver RT None IRQ14 IRQ15 S RT IOCHCK# None STOP RT STOP FRAME H I START NEXT CYCLE 1 2 3 FRAME FRAME FRAME Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame. Note 2: There may be none, one or more Idle states during the Stop Frame. Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. |
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