LPC47M14X datasheet(23/205 Pages) SMSC

23 / 205 page

SMSC DS – LPC47M14X

Page 23

Rev. 03/19/2001

SYNC Patterns and Maximum Number of SYNCS

If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.

If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M14x has protection

mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout

protection that is in EPP.

SYNC Error Indication

The LPC47M14x reports errors via the LAD[3:0] = 1010 SYNC encoding.

If the host was reading data from the LPC47M14x, data will still be transferred in the next two nibbles. This data may

be invalid, but it will be transferred by the LPC47M14x. If the host was writing data to the LPC47M14x, the data had

already been transferred.

In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is

transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not

be transferred.

I/O and DMA START Fields

I/O and DMA cycles use a START field of 0000.

Reset Policy

The following rules govern the reset policy:

When PCI_RESET# goes inactive (high), the clock is assumed to have been running for 100usec prior to the

removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable

that is used for the PCI bus.

When PCI_RESET# goes active (low):

The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal.

The LPC47M14x must ignore LFRAME#, tristate the LAD[3:0] pins and drive the LDRQ# signal inactive (high).

6.3.10

LPC Transfer

Wait State Requirements

I/O Transfers

The LPC47M14x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110

is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in

an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used and a large number of

syncs may be inserted (up to 330 which corresponds to a timeout of 10us).

DMA Transfers

The LPC47M14x inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of

0101 is used for all DMA transfers.

See the example timing for the LPC cycles in the “Timing Diagrams” section.

LPC47M14X 数据表(PDF) 23 Page - SMSC Corporation

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