LPC47M14X datasheet(28/205 Pages) SMSC

28 / 205 page

SMSC DS – LPC47M14X

Page 28

Rev. 03/19/2001

PS/2 Model 30 Mode

BIT 0 DIRECTION

Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1"

indicates outward direction.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active,

and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DMA request pending.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt.

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The

SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a

high impedance state for a read of address 3F1.

PS/2 Mode

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a

software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a

software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

INT

PENDING

DRQ

STEP

F/F

TRK0 nHDSEL INDX

nDIR

RESET

COND.

N/A

DRIVE

SEL0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE

MOT

EN1

MOT

EN0

RESET

COND.

LPC47M14X 数据表(PDF) 28 Page - SMSC Corporation

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