LPC47M14X datasheet(7/205 Pages) SMSC

7 / 205 page

SMSC DS – LPC47M14X

Page 7

Rev. 03/19/2001

FIGURES

FIGURE 1 – LPC47M14X BLOCK DIAGRAM...........................................................................................................16

FIGURE 2 – LPC47M14X CLOCK GENERATOR .....................................................................................................24

FIGURE 3 – MPU-401 MIDI INTERFACE..................................................................................................................73

FIGURE 4 – MPU-401 INTERRUPT ..........................................................................................................................76

FIGURE 5 - MIDI DATA BYTE EXAMPLE ...................................................................................................................77

FIGURE 6 – KEYBOARD LATCH ............................................................................................................................108

FIGURE 7 – MOUSE LATCH...................................................................................................................................108

FIGURE 8 – GPIO FUNCTION ILLUSTRATION......................................................................................................112

FIGURE 9 – POWER-UP TIMING ...........................................................................................................................178

FIGURE 10 – DATA SIGNAL RISE AND FALL TIME ..............................................................................................180

FIGURE 11 – FULL SPEED LOAD ..........................................................................................................................180

FIGURE 12 – LOW-SPEED PORT LOADS .............................................................................................................180

FIGURE 13 – CABLE DELAY ..................................................................................................................................180

FIGURE 14 – DIFFERENTIAL DATA JITTER..........................................................................................................181

FIGURE 15 – DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH...................................................181

FIGURE 16 – RECEIVER JITTER TOLERANCE ....................................................................................................181

FIGURE 17 – INPUT CLOCK TIMING .....................................................................................................................182

FIGURE 18 – PCI CLOCK TIMING..........................................................................................................................182

FIGURE 19 – RESET TIMING .................................................................................................................................182

FIGURE 20 – OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.................................................183

FIGURE 21 – INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.....................................................183

FIGURE 22 – I/O WRITE .........................................................................................................................................184

FIGURE 23 – I/O READ...........................................................................................................................................184

FIGURE 24 – DMA REQUEST ASSERTION THROUGH LDRQ#...........................................................................185

FIGURE 25 – DMA WRITE (FIRST BYTE) ..............................................................................................................185

FIGURE 26 – DMA READ (FIRST BYTE)................................................................................................................185

FIGURE 27 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) ...........................................................................186

FIGURE 28 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE .................................................................................187

FIGURE 29 – EPP 1.9 DATA OR ADDRESS READ CYCLE ..................................................................................188

FIGURE 30 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE .................................................................................189

FIGURE 31 – EPP 1.7 DATA OR ADDRESS READ CYCLE ..................................................................................189

FIGURE 32 – PARALLEL PORT FIFO TIMING .......................................................................................................191

FIGURE 33 – ECP PARALLEL PORT FORWARD TIMING ....................................................................................191

FIGURE 34 – ECP PARALLEL PORT REVERSE TIMING......................................................................................192

FIGURE 35 – IRDA RECEIVE TIMING....................................................................................................................193

FIGURE 36 – IRDA TRANSMIT TIMING .................................................................................................................194

FIGURE 37 – AMPLITUDE SHIFT KEYED IR RECEIVE TIMING ...........................................................................195

FIGURE 38 – AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ........................................................................196

FIGURE 39 – SETUP AND HOLD TIME..................................................................................................................197

FIGURE 40 – SERIAL PORT DATA ........................................................................................................................197

FIGURE 41 – JOYSTICK POSITION SIGNAL.........................................................................................................197

FIGURE 42 – JOYSTICK BUTTON SIGNAL ...........................................................................................................197

FIGURE 43 – KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING .....................................................................198

FIGURE 44 – MIDI DATA BYTE ..............................................................................................................................198

FIGURE 45 – FAN OUTPUT TIMING ......................................................................................................................199

FIGURE 46 – FAN TACHOMETER INTPUT TIMING ..............................................................................................199

FIGURE 47 – LED OUTPUT TIMING ......................................................................................................................199

FIGURE 48 – 128 PIN QFP PACKAGE OUTLINE...................................................................................................200

FIGURE 49 – XNOR-CHAIN TEST STRUCTURE...................................................................................................201

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