LPC47M14X datasheet(69/205 Pages) SMSC

69 / 205 page

SMSC DS – LPC47M14X

Page 69

Rev. 03/19/2001

Table 32 – Reset Function Table

RESET CONTROL

RESET STATE

Interrupt Enable Register

RESET

All bits low

Interrupt Identification Reg.

RESET

Bit 0 is high; Bits 1 - 7 low

FIFO Control

RESET

All bits low

Line Control Reg.

RESET

All bits low

MODEM Control Reg.

RESET

All bits low

Line Status Reg.

RESET

All bits low except 5, 6 high

MODEM Status Reg.

RESET

Bits 0 - 3 low; Bits 4 - 7 input

TXD1, TXD2

RESET

High

INTRPT (RCVR errs)

RESET/Read LSR

Low

INTRPT (RCVR Data Ready)

RESET/Read RBR

Low

INTRPT (THRE)

RESET/ReadIIR/Write THR

Low

OUT2B

RESET

High

RTSB

RESET

High

DTRB

RESET

High

OUT1B

RESET

High

RCVR FIFO

RESET/

FCR1*FCR0/_FCR0

All Bits Low

XMIT FIFO

RESET/

FCR1*FCR0/_FCR0

All Bits Low

Table 33 – Register Summary for an Individual UART Channel

ADDRESS*

SYMBOL

BIT 0

BIT 1

ADDR = 0

DLAB = 0

Receive Buffer Register (Read Only)

RBR

Data Bit 0

(Note 1)

Data Bit 1

ADDR = 0

DLAB = 0

Transmitter Holding Register (Write

Only)

THR

Data Bit 0

Data Bit 1

ADDR = 1

DLAB = 0

Interrupt Enable Register

IER

Enable

Received

Data

Available

Interrupt

(ERDAI)

Enable

Transmitter

Holding

Empty

Interrupt

(ETHREI)

ADDR = 2

Interrupt Ident. Register (Read Only)

IIR

"0" if

Interrupt

Pending

Interrupt ID

Bit

ADDR = 2

FIFO Control Register (Write Only)

FCR

(Note 7)

FIFO Enable RCVR FIFO

Reset

ADDR = 3

Line Control Register

LCR

Word

Length

Select Bit 0

(WLS0)

Word

Length

Select Bit 1

(WLS1)

ADDR = 4

MODEM Control Register

MCR

Data

Terminal

Ready

(DTR)

Request

Send (RTS)

ADDR = 5

Line Status Register

LSR

Data Ready

(DR)

Overrun

Error (OE)

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