LPC47M14X datasheet(89/205 Pages) SMSC

89 / 205 page

SMSC DS – LPC47M14X

Page 89

Rev. 03/19/2001

BIT 6 intrValue

Returns the value of the interrupt to determine possible conflicts.

BIT [5:3] Parallel Port IRQ (read-only)

to Table 45B

BITS [2:0] Parallel Port DMA (read-only)

to Table 45C

ECR (Extended Control Register)

ADDRESS OFFSET = 402H

Mode = all

This register controls the extended ECP parallel port functions.

BITS 7,6,5

These bits are Read/Write and select the Mode.

BIT 4 nErrIntrEn

Read/Write (Valid only in ECP Mode)

Disables the interrupt generated on the asserting edge of nFault.

Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is

asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time

between the read of the ecr and the write of the ecr.

BIT 3 dmaEn

Read/Write

Enables DMA (DMA starts when serviceIntr is 0).

Disables DMA unconditionally.

BIT 2 serviceIntr

Read/Write

Disables DMA and all of the service interrupts.

Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit

shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause

an interrupt.

case dmaEn=1:

During DMA (this bit is set to a 1 when terminal count is reached).

case dmaEn=0 direction=0:

This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO.

case dmaEn=0 direction=1:

This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO.

BIT 1 full

Read only

The FIFO cannot accept another byte or the FIFO is completely full.

The FIFO has at least 1 free byte.

BIT 0 empty

Read only

The FIFO is completely empty.

The FIFO contains at least 1 byte of data.

LPC47M14X 数据表(PDF) 89 Page - SMSC Corporation

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